Skhynix Inc.

Korea Advanced Institute of Science and Technology

Young-Suk Moon

Hong-Sik Kim

Yong-Kee Kwon

Hyung-Dong Lee

Hyung-Gyun Yang

Won-Gyu Shin

Lee-Sup Kim

Jung-Whan Choi

Jung-Hyun Kwon

Dong-Gun Kim

Seung-Gyu Jeong

Kyung-min Lee

Joon-Woo Kim

Young-Jae Jin

Disclosed herein is a convolutional neural network (CNN) operation apparatus, including at least one channel hardware set suitable for performing a feature extraction layer operation and a classification layer operation based on input data and weight data, and a controller coupled to the channel hardware set. The controller may control the channel hardware set to perform the feature extraction layer operation and perform a classification layer operation when the feature extraction layer operation is completed.

Operation apparatus and method for convolutional neural network

In a cache memory used for communication between a host and a memory, the cache memory may include a plurality of cache sets, each comprising: a valid bit; N dirty bits; a tag; and N data sets respectively corresponding to the N dirty bits and each including data of a data chunk size substantially identical to a data chunk size of the host, wherein a data chunk size of the memory is N times as large as the data chunk size of the host, where N is an integer greater than or equal to 2.

Cache memory, memory system including the same, and eviction method of cache memory

A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. The memory system may include a memory controller configured to control the memory buffer chip to input/output data to/from the one or two or more memory chips. The memory buffer chip may include a first interface configured to transmit/receive a signal to/from the memory controller. The memory buffer chip may include a second interface configured to transmit/receive a signal to/from the memory chip. The memory buffer chip may include a command buffer configured to buffer commands received from the memory controller through the first interface. The memory buffer chip may include a read buffer configured to buffer read data received from the memory chip.

Memory buffer chip, memory system and method of controlling the memory buffer chip

An integrated circuit system includes a host device; and a memory module suitable for communicating with the host device according to a first protocol, the memory module comprising: at least one memory device suitable for storing data or outputting stored data, and executing communication according to a second protocol; and a protocol converter suitable for transferring information among the host device and the at least one memory device, wherein information to be inputted to the at least one memory device is transferred by being converted according to the second protocol and information to be outputted from the at least one memory device is transferred by being converted according to the first protocol.

Integrated circuit system

In an embodiment a memory chip may be provided. The memory chip may include a chip select buffer configured to receive a chip select signal, a command buffer configured to receive a command signal, wherein the command signal is input after a time has elapsed since the chip select signal is activated and the command buffer is turned on when the command signal is input.

Memory chip with reduced power consumption, buffer chip module controlling the same and memory module including the same

Memory controller, memory buffer chip and memory system

A memory controller includes a plurality of request queues for storing requests transmitted from corresponding host devices among a plurality of host devices, and a token information generation unit for generating information related to the numbers of first and second tokens corresponding to the plurality of respective host devices. The memory controller also includes a request scheduler for selecting repeatedly and sequentially the plurality of request queues, and outputting requests stored in a selected request queue, by using the first and second tokens, wherein the request scheduler outputs one request per one first token and, when first tokens are all consumed, outputs one request per one second token. The scheduler may output requests according to a first-ready first-come first-served (FR-FCFS) rule when using a first token, and output requests according to a first-ready (FR) rule when using a second token. The number of first tokens and second tokens may depend on characteristics of the host devices. A bandwidth control unit may control the number of first and second tokens based on bandwidth. The scheduler may stop outputting requests of a currently selected request queue, and output requests of a request queue corresponding to a top-priority host device.

Memory controller and request scheduling method using request queues and first and second tokens

A semiconductor device may include a first address cache configured to store a physical address of a semiconductor memory device and a write count associated with the physical address, an address monitor configured to update the physical address and the write count in the first address cache based on a received write request, and an arbiter configured to store a write address and write data associated with the write request in a write cache in response to a command from the address monitor, wherein the command generated by the address monitor is based on whether an update is made to the physical address and the write count in first address cache.

Semiconductor device configured to control a wear leveling operation and operating method thereof

A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.

Memory controller

A semiconductor system may include a plurality of memory devices corresponding to a plurality of channels, an address mapping unit suitable for converting addresses corresponding to provided external requests according to a selected address map among a plurality of address maps; a monitoring unit suitable for monitoring the external requests provided to each of the plurality of channels, and a control unit suitable for providing a control signal for controlling the address mapping unit to select an address map according to a result of the monitoring.

Semiconductor system and operating method thereof

A memory controller schedules requests to memory devices according to scores. For this purpose, the memory controller variably adjusts weights for determining the scores with respect to the requests, calculates the scores using the weights, and determines a processing order of the requests according to the scores. The memory controller includes a request queue, a scheduler, and a weight generation circuit. The request queue stores the requests provided from an external device. The scheduler calculates a score for each request included in the request queue and determines the processing order of the requests based on the scores for the requests. The weight generation circuit generates a weight vector including the weights used to calculate the scores.

Memory controller scheduling requests according to scores

A semiconductor device may include: a storage unit configured to store program codes provided through control of a processor core; and a control unit configured to perform a control operation on a semiconductor memory device according to the program codes.

Semiconductor device for performing test and repair operations

A semiconductor device includes a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when the multi-bit error has occurred.

Semiconductor device and operating method thereof

A semiconductor device comprises: a read queue configured to store one or more read requests to a semiconductor memory device; a write queue configured to store one or more write requests to the semiconductor memory device; and a dispatch block configured to determine a scheduling order of the one or more read requests and the one or more write requests and switch to the read queue or to the write queue if a request exists in a Row Hit state in the read queue or in the write queue.

Growing community of inventors

Icheon-si, South Korea

Young-Suk Moon