Skhynix Inc.

Young Sub Yuk

Young Jin Moon

Seung Wan Chai

Jae Woo Song

A semiconductor chip includes a detection circuit configured to generate a discharge signal that is enabled when a voltage level of an external voltage is greater than a first set level and configured to generate a voltage control signal that is enabled when an output voltage is generated to have a voltage level of a ground voltage in a test mode, a charge discharge circuit configured to discharge charges of an output node that is included in a driving circuit when the discharge signal is enabled, and the driving circuit configured to generate the output voltage the voltage level of which rises up to a second set level by supplying charges from the external voltage to the output node in response to a driving signal a voltage level of which is decreased during an interval in which the voltage control signal is enabled.

Semiconductor chip and semiconductor system

A reference voltage generation circuit may include: a first reference current path formed through a first node and a first transistor; a second reference current path formed through a second node and a second transistor; a first feedback loop configured to feed a first current back to the first and second reference current paths such that voltage levels of the first and second nodes are kept the same; and a second feedback loop configured to control the currents flowing through the first and second transistors according to a second current.

Reference voltage generation circuit

A data storage apparatus includes storage, and a controller including an internal voltage trimming circuit and controlling the storage in response to a request from a host. The trimming circuit may include an integral circuit sampling a difference between a test voltage output by a device under test and a reference voltage, generating an integral signal by integrating a sampled signal, and including an offset cancellation unit cancelling an offset from the sampled signal, a comparison circuit generating a comparison signal by comparing the integral signal with the reference voltage, a code generation circuit receiving an initial trimming code and generating preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal, and a code average signal generation circuit generating the final trimming code by averaging the preliminary trimming codes for a given time and provide the final trimming code to the storage.

Data storage apparatus, and internal voltage trimming circuit and trimming method therefor

There are provided a signal generation circuit and a semiconductor memory device including the same. The signal generation circuit includes: a signal input component configured to generate a first internal output signal and a second internal output signal in response to an input signal, and to adjust potential levels of the first internal output signal and the second internal output signal in response to an output signal; and a signal output component configured to generate the output signal in response to the first internal output signal and the second internal output signal.

Signal generation circuit and semiconductor memory device including the same

A sensing buffer, or peripheral circuit or memory device may be provided. The sensing buffer may be configured to maintain a predetermined current according to a first current regardless of an external power supply and/or a temperature.

Growing community of inventors

Gyeonggi-do, South Korea

Young Sub Yuk