Samsung Electronics Co., Ltd.

Other

Postech Foundation

Young-Soo Sohn

Kwang-il Park

Chul-woo Park

Seung-Jun Bae

Jong-Pil Son

Jae-Youn Youn

Kyung-Soo Ha

Ki-Seok Oh

Uk-Song Kang

Su-a Kim

Tae-young Kim

Tae-Young Oh

Hak-soo Yu

Donghun Lee

Seok-Hun Hyun

Dong-min Kim

Chang-Kyo Lee

Yeon-Kyu Choi

Changkyo Lee

Young-Hoon Son

Sei-jin Kim

Dae-Sik Moon

Jin-Hoon Jang

Ho-Seok Seol

Si-Hong Kim

Hyun-Yoon Cho

Daesik Moon

Seokhun Hyun

Kyo-Min Sohn

Dae-hyun Kim

Hoi-ju Chung

Jae-Sung Kim

Jin-il Lee

Jung-hwan Choi

Ho-Sung Song

Jeong-Don Lim

Hong-June Park

Young-Sik Kim

Jung-Hwan Choi

Jung-Bae Lee

Dong-Min Kim

Jung Hwan Choi

Jeong-Don Ihm

Woo-Jin Lee

Dae-Jeong Kim

Cheol Su Kim

Kyoung-Ho Kim

Chan-kyung Kim

Won-Il Bae

Sang-Yun Kim

Su-Yeon Doo

Sang-Ho Shin

Sang-hyup Kwak

Hyo-jin Choi

Jae-Hyung Lee

Ki-Heung Kim

Sung-Hyun Lee

Kwang-II Park

In-soo Park

Dong-Soo Kang

Dae-Sun Kim

Kyoung-Heon Jeong

Jun-Hee Yoo

Hong-Jun Park

Hye-Yoon Joo

Sung-Min Ryu

Cheol-Heui Park

Yun-Seok Yang

A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Memory device, memory system, and operation method of memory device

A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Method and memory system for optimizing on-die termination settings of multi-ranks in a multi-rank memory device

Memory device performing ZQ calibration, memory system, and operation method of memory device

An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

Integrated circuit memory devices having buffer dies and test interface circuits therein that support testing and methods of testing same

A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

Memory device that performs internal copy operation

Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a 'fail' cell by using an error correction code (ECC) operation, and also repairs the 'fail' cell by using a redundancy repair operation when the &#x2018;fail&#x2019; cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the &#x2018;fail&#x2019; cell, and may also change the size of parity bits regarding the changed codeword.

Memory device for performing error correction code operation and redundancy repair operation

A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Semicondutor memory device and memory system including the same

A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data.

Method of use time management for semiconductor device and semiconductor device including use time managing circuit

A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Memory device and memory system having the same

A memory device, system, and/or method are provided for performing a page state informing function. The memory device may compare one or more row addresses received along with a command, determine the page open/close state according to a page hit or miss generated as a result of comparison, count read or write commands with respect to pages corresponding to a same row address, and determine the page open/close state according to a read or write command number generated as a result of counting. The memory device may determine a page open/close state with respect to a corresponding page based on a page hit/miss and a read or write command number and output a flag signal. The memory device may provide the page open/close state for each channel. A memory controller may establish different page open/close policies for each channel.

Memory device having page state informing function

Growing community of inventors

Seoul, South Korea

Young-Soo Sohn