Electronics and Telecommunications Research Institute

Young Soo Park

Sung Ik Jun

Ji Man Park

Young Sae Kim

Yong Tae Lee

Moo Seop Kim

Won Geun Ryu

Jong Soo Jang

Kyo Il Chung

Sang Woo Lee

Eui Suk Jung

Yun Kyung Lee

Jung Hak Kim

Sung Won Sohn

Young Il Kim

Ho Won Kim

Eun Jung Kwon

Won Joo Park

Seung Hee Kim

Hong Il Ju

Sang Yun Lee

Hyun Ho Park

Myung Sun Baek

Sung Won Byon

Yong Je Choi

Heui Su Ryu

A crime type inference system based on text data, may include: a keywords dictionary construction unit configured to receive crime source data, and generate a crime type keywords dictionary by extracting crime keywords; a data set construction unit configured to generate a dataset for crime type learning by using the crime source data and the keywords dictionary; a crime type prediction model training unit configured to generate a crime type prediction model by using the dataset, and train the crime type prediction model; and a crime type inference unit configured to infer a crime type by using new crime data.

Crime type inference system and method based on text data

A network cooperation-based low power type charged broadcasting set-top box and a controlling method therefor, the set-top box sub-dividing a standby mode of the set-top box into an active standby mode, in which only background functions are processed without processing a main function, and a passive standby mode, in which no functions are processed; extending the passive standby mode occupation time to more than that of the active standby mode; and including a way of transitioning between operating modes by exchanging information regarding the set-top box through an inter-cooperation between a charged broadcasting network and the set-top box, thereby reducing the power consumption of a processor (SoC) which processes multimedia contents and minimizing the power consumption while the set-top box is in standby mode.

Network cooperation-based low power type charged broadcasting set-top box and controlling method therefor

A method of acquiring an Internet protocol (IP) address to control a standby mode of a set-top box, and the set-top box and a power management server performing the method are disclosed. The method may include determining whether a state of the set-top box changes from a broadcasting state in which a broadcasting service is provided to a passive standby state in which a network connection between the set-top box and a headend providing the broadcasting service is blocked, receiving state information associated with an IP address allocated to the set-top box for the network connection in response to the state of the set-top box changing to the passive standby state, and transmitting, to the set-top box, a state change command to maintain the network connection for the IP address allocated to the set-top box based on the received state information.

IP address acquisition method for controlling standby mode of set-top box, and set-top box and power management server performing the method

An apparatus for hash cryptography has a hardware structure that is capable of providing both secure hash algorithm (SHA)-1 hash calculation and SHA-256 hash calculation. The apparatus for hash cryptography generates a plurality of first message data corresponding to a plurality of first rounds when the SHA-1 hash calculation is performed and generates a plurality of second message data corresponding to a plurality of second rounds when the SHA-256 hash calculation is performed by using one memory, one first register, one XOR calculator, and one OR calculator, calculates a message digest by the SHA-1 hash calculation by using the plurality of first message data when the SHA-1 hash calculation is performed, and calculates a message digest by the SHA-256 by using the plurality of second message data when the SHA-256 hash calculation is performed.

Apparatus and method for hash cryptography

A sensor signal processor apparatus having good characteristics and providing an easy and simple interface for various sensors. The sensor signal processor apparatus includes a current source, a sensor, a ramp integrator, a comparator, and a controller. The current source generates a constant current according to a preset value, and the sensor outputs a sensor voltage using the current from the current source. The ramp integrator generates and outputs an integral voltage according to an input command, and the comparator compares the sensor voltage of the sensor with the integral voltage of the ramp integrator and outputting a result of the comparison. The controller controls the generating and outputting of the integral voltage of the ramp integrator according to the comparison result of the comparator.

Sensor signal processor apparatus

There are provided a low power SHA-1 hash algorithm apparatus having a low power structure and optimized to a trusted platform module (TPM) applied to a mobile trusted computing environment and a low power keyed-hash message authentication code (HMAC) encryption apparatus using the low power SHA-1 hash algorithm apparatus, the HMAC encryption apparatus including: a key padder padding key data for HMAC algorithm; an XOR operator XOR operating the padded key data and a padding constant; a data connector connecting a text to be encrypted, to data obtained by the XOR operating; a data padder padding the connected data; an SHA-1 hash algorithm part performing an SHA-1 hash algorithm on the padded data; a data selector selecting and applying one of a result of the SHA-1 hash algorithm and the text to be encrypted, to the data connector; and a controller controlling operations of the key padder, data connector, and data padder, a sequence of performing a hash algorithm of the SHA-1 hash algorithm part, and storing an operation result to read data required for performing an encryption operation and store data with memory.

Low power HMAC encryption apparatus

A double-integration signal processing apparatus for pulse width amplification and A/D conversion is provided. The current mode double-integration conversion apparatus includes: a current mode double-integration unit which integrates an input current in a predetermined time interval and outputs an integration voltage; a comparison unit which compares the integration voltage output from the current mode double-integration unit with a predetermined comparison voltage V k and outputs an comparison pulse signal; and a gate logic unit which performs a logic operation by using the comparison pulse signal of the comparison unit and an internal signal and outputs an logic operation pulse signal. Accordingly, the current mode double-integration conversion apparatus can be applied to various sensors.

Current mode double-integration conversion apparatus

A rijndael block cipher apparatus including an operational unit that efficiently performs a round operation for encrypting/decrypting a rijndael block cipher and an encryption/decryption method thereof are disclosed. The rijndael block cipher apparatus is mounted in a mobile terminal such as a cellular phone and a PDA or a smart card, which requires a high-rate and small-sized cipher processor, and can encrypt and decrypt important data that requires security at high speed and perform the round operation with respect to upper 64 bits and lower 64 bits which are divided from 128-bit input data. Thus, the cipher apparatus can reduce the time required for encryption/decryption of the rijndael block cipher and the size of the apparatus.

Rijndael block cipher apparatus and encryption/decryption method thereof

An apparatus and method for computing a SHA-1 hash function value are provided. The apparatus includes a first register unit including a plurality of registers that store a first bit string of predetermined lengths for generation of a hash function value; a second register unit storing input data in units of second bit strings with predetermined lengths, and sequentially outputting the second bit strings; a third register unit performing an operation on the first bit string of the plurality of registers and the second bit strings output from the second register unit so as to generate and store a third bit string, and updating first-bit string of the plurality of registers based on the third bit string; and an adding unit combining the first bit string stored in the first register unit, the first bit string of the third bit string stored in the third register unit, and the original initial values stored in the first register unit so as to obtain a hash function value. Accordingly, it is possible to reduce the size of the apparatus and stably compute a hash function value at a high speed.

Apparatus and method for computing SHA-1hash function

Disclosed is an RSA cryptographic processing apparatus capable of performing the fast operating function. A modular multiplication operation or a modular exponentiation operation, i.e., an RSA cryptographic operation, is selectively performed according to a control signal inputted, the modular operation of the data of 512 to 1024 bits is iteratively performed by use of 32-bit operating unit, and the data of 512 to 1024 bits is operated by use of a 32-bit operating unit, thereby minimizing the size of the register storing the data and reducing the size of the cryptographic apparatus, and which the intermediate value generated at the operation process is stored in the internal register instead of the memory, thereby minimizing the times of access to the memory.

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Daejeon, South Korea

Young Soo Park