Skhynix Inc.

Young Sik Koh

Seung Jin Park

Chang Kyun Park

Dong Hyun Lee

A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

Memory system and operating method of the memory system

The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit, the interface circuit storing first system data, and a semiconductor memory; and a controller configured to output a read enable signal and a first read command for the first system data to the memory device. The semiconductor memory transfers a data strobe signal to the interface circuit in response to the read enable signal, the interface circuit reads the first system data in response to the first read command and transmits the read first system data to the controller in synchronization with the data strobe signal.

Memory system capable of improving stability of a data read operation of interface circuit, and method of operating the memory system

The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller configured to generate a command set in response to a host command and output the command set to the memory device. The interface circuit is configured to: receive the command set, transmit the received command set to the semiconductor memory, when the received command set corresponds to the semiconductor memory, perform a blocking operation so that the received command set is not transmitted to the semiconductor memory, when the received command set corresponds to the interface circuit, and perform an on-die termination operation, a ZQ calibration operation, or a driving force control operation of the interface circuit in response to the received command set corresponding to the interface circuit.

Memory system and method of operating the memory system

Provided is a method for operating an interface circuit of a memory device. The method includes receiving a command from a controller; determining whether the command is for a semiconductor memory or the interface circuit, the semiconductor memory operatively coupled to the interface circuit; and when it is determined that the command is for the interface circuit, performing a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performing an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

The present technology includes a memory device and a method of operating the same. The memory device in which an interface circuit and a semiconductor memory are packaged together includes a centrally located region in a ball mapping region of a memory device in which data input/output pins for an operation of the interface circuit and the semiconductor memory are disposed, and a test pin region in which test pins for a test operation of the interface circuit are disposed.

Memory device and test operation method thereof

The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller configured to generate a command for controlling the memory device and output the command to the memory device. The interface circuit receives the command, transmits the received command to the semiconductor memory when the received command corresponds to the semiconductor memory, and performs a training operation of the interface circuit when the received command corresponds to the interface circuit and the received command is a specific command.

Growing community of inventors

Gyeonggi-do, South Korea

Young Sik Koh