Skhynix Inc.

Young Seung Yoo

Hyung Jin Choi

In Gon Yang

Chan Keun Kwon

Sung Hwa Ok

Hyeon Cheon Seol

Ja Yoon Goo

Ji Seong Mun

A memory device includes a plurality of memory planes, each including a plurality of memory banks; one or more plane groups, each comprising at least two memory planes sharing at least one peripheral circuit; a plurality of compressing circuits, each connected to a corresponding memory bank and outputting compressed data by compressing data read from the corresponding memory bank; a plurality of merge circuits, each receiving compressed data and at least one output control signal corresponding to a merge group of a plurality of merge groups, each merge circuit outputting, in response to at least one output control signal, merged data obtained by merging compressed data corresponding to memory banks grouped in the merge group; and an output buffer circuit latching and outputting the merged data in response to at least one output control signal. The merge group comprises at least two memory banks in a same plane group.

Memory device, operating method of memory device, and storage device

A semiconductor device may include a page buffer comprising first to fifth latches, wherein the first to third latches and the fifth latch are configured to store 4-bit original data, among 5-bit original data, respectively, and the fourth latch is configured to store data identical with the data that has been stored in the second latch and a control circuit configured to determine a program inhibition pattern based on data that have been stored in two of the first to fifth latches and control the page buffer so that data that has been stored in at least one of the first to fifth latches is inverted based on the program inhibition pattern.

Semiconductor device and operating method with page buffer including latches

A semiconductor device may include a memory cell array including a memory block including a plurality of memory strings connected between a plurality of bit lines and a common source line, a control circuit that generates a page buffer control signal, a voltage control signal, and a drive address signal, a page buffer group including a plurality of page buffers and configured to form each of the plurality of bit lines to a preset voltage level, and generate a threshold voltage variation result on the basis of a change in the voltage level of each of the plurality of bit lines, a voltage generation circuit that generates a threshold verification voltage and a pass voltage, and a line drive circuit that drives a plurality of select lines to a level of the threshold verification voltage, and drives a plurality of word lines to a level of the pass voltage, during the threshold voltage variation verification.

Semiconductor device capable of checking deterioration of select transistor and operating method thereof

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Gyeonggi-do, South Korea

Young Seung Yoo