Adtechnology Co., Ltd.

Young Seung Kim

Min Chul Jung

Seung Moon Yoo

Dong Min Lim

Jun Suk Kim

Scott Seungmoon Yoo

Mi Hwa Lim

A memory device may comprise: a memory cell array in which memory cells are connected in matrix form to word lines and bit lines; a plurality of mergers connected in series to transfer data that is read from a selected memory cell among the memory cells included in the memory cell array and is transformed into one of a direct current form or a pulse form; and an aligner that synchronizes an edge of first output data, output by one of the plurality of mergers, with an edge of a control pulse, thereby delaying the edge of the first output data.

Memory device with data mergers and aligner

A memory device according to the present invention may comprise: a memory cell array in which memory cells of a latch structure are connected in matrix form to word lines and bit line pairs composed of bit lines and inverted bit lines; and a driving circuit which, during an ON period in which the word lines activate first memory cells connected to the corresponding word lines, continuously programs or reads n (n is a natural number of 2 or more) second memory cells among the first memory cells through n first bit line pairs.

Memory device, and method for driving memory

A memory device according to the present invention comprises: a memory cell array in which memory cells are connected to wordlines and bitlines in a matrix form; and a control circuit for programming the memory cells or controlling a read operation, according to a start address, a burst length, a latency length, and a program or read command which are transmitted from a host, wherein the control circuit may comprise: a pulse generation unit for generating register pulses and counter pulses in synchronization with an operation clock; and a counter that sets the start address in synchronization with the register pulses, counts the number of counter pulses corresponding to the sum of the latency length and the burst length, and increases an address from the start address to the sum of the start address and the burst length.

Integrated counter in memory device

Disclosed herein is a latch circuit capable of preventing an output failure caused due to simultaneous transition of a control signal and an input signal. The latch circuit according to the present invention generates a separate control adjustment signal CTR using the control signal Control and the input signal In and uses the control adjustment signal CTR, instead of the control signal for a latch operation. Accordingly, when the control signal and the input signal transition at the same time, the control adjustment signal is processed not to transition during a transition interval of the input signal, thereby preventing a metastability problem that occurred in the existing latch circuit.

Growing community of inventors

Seoul, South Korea

Young Seung Kim