Skhynix Inc.

Young Seok Ko

Soo Gil Kim

Joo Young Moon

Hyun Min Lee

Hyun Jin Lee

Jung Hun Lee

A method for forming a semiconductor device is disclosed. The method for forming the semiconductor device includes forming a first sacrificial film over a target layer to be etched, forming a first partition mask over the first sacrificial film, forming a first sacrificial film pattern by etching the first sacrificial film using the first partition mask, forming a first spacer at a sidewall of the first sacrificial film pattern, and forming a first spacer pattern by removing the first sacrificial film pattern. The first partition mask includes a plurality of first line-shaped space patterns extending in a first direction. A width of at least one space pattern located at both edges from among the plurality of first space patterns is smaller than a width of each of other space patterns.

Method for manufacturing semiconductor device

An electronic device may include a semiconductor memory. The semiconductor memory may include: row lines; column lines intersecting the row lines; memory cells located in intersection regions of the row lines and the column lines, the memory cells including upper and lower electrodes; and interface layers located between the lower electrodes of the memory cells and the row lines, the interface layers having a width narrower than that of the row lines.

Electronic device and method for fabricating electronic device

In an embodiment, a substrate that includes a cell region and a dummy region is provided. Lower interconnection structures are formed in the cell region and the dummy region. One or more first multilayered structure patterns are formed in the cell region and one or more second multilayered structure patterns in the dummy region over the lower interconnection structures. The first multilayered structure patterns and second multilayered structure patterns extend in a first direction. Each of the second multilayered structure patterns includes an etch target layer. An insulating material layer is formed over the first multilayered structure patterns and the second multilayered structure patterns. An interlayer insulating layer that fills a space between two adjacent patterns of the first multilayered structure patterns and second multilayered structure patterns is formed by planarizing the insulating material layer. The etch target layer in each of the second multilayered structure patterns is removed.

Growing community of inventors

Suwon, South Korea

Young Seok Ko