Samsung Electronics Co., Ltd.

Young-Sam Park

Seung-Beom Yoon

Jeong-Uk Han

Sung-Taeg Kang

Seung-Jin Yang

Yong-Tae Kim

Yong-suk Choi

Jae-Hwang Kim

A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region along the circumference of the semiconductor body, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, electrically insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate.

Nonvolatile semiconductor device and method of fabricating the same

A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.

Silicon-oxide-nitride-oxide-silicon (SONOS) devices and methods of manufacturing the same are provided. According to one aspect, a SONOS device includes a semiconductor substrate having a first surface, a second surface of lower elevation than the first surface, and a third surface perpendicular and between the first and second surfaces; a tunnel dielectric layer on the semiconductor substrate; a charge trapping layer in a form of a spacer on the tunnel dielectric layer on the third surface; a charge isolation layer on the tunnel dielectric layer, which covers the charge trapping layer; a gate that extends over a portion of the first surface, over a portion of the second surface, and is adjacent to a portion of the third surface of the semiconductor substrate on the charge isolation layer; a first impurity region formed below the first surface and near the gate; and a second impurity region formed below the second surface, opposite the first impurity region.

Sonos device and methods of manufacturing the same

A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.

Growing community of inventors

Suwon-si, South Korea

Young-Sam Park