Skhynix Inc.

Young Ook Song

Chang Hyun Kim

Yong Mi Kim

Su Hae Woo

Hyun Seok Kim

Sung Eun Lee

A memory system includes a memory device including banks each including a plurality of rows, and configured to select, within a selected bank of the banks, at least one row from the plurality of rows based on a target address; and a row-hammer tracking module configured to: select the selected bank based on a pattern of accesses to each of the banks, and select the target address according to an access number for each of a plurality of groups of the rows within the selected bank.

Memory controller, memory system and operation of row-hammer tracking

A memory system includes a plurality of memory devices; and a memory controller configured to perform an initial training operation to set a plurality of time codes corresponding to the plurality of memory devices, respectively, receive a plurality of data signals read from the plurality of memory devices, as internal data signals, according to the plurality of time codes, respectively, and adjust the plurality of time codes based on the internal data signals and error pattern maps generated by collecting error location information for the internal data signals.

Controller, memory system and operating method of memory system

A parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity in a first error correction mode having a first error correction capability for original data. The second parity generation part is configured to generate a second parity using the first parity in a second error correction mode having a second error correction capability.

Parity generation circuits for a plurality of error correction levels, memory controllers, and memory modules including the parity generation circuits

A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.

Methods of scrubbing errors and semiconductor modules using the same

A semiconductor system may be provided. The semiconductor system may include a fail information generator and a data mapping circuit. The fail information generator may detect a data fail address of a data storage region. The data mapping circuit may change a mapping table based on the data fail address, and transmit data to be stored at the data fail address in the data storage region, to a parity storage region.

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Seoul, South Korea

Young Ook Song