Skhynix Inc.

Young-Ook Song

Yong-Ju Kim

Jung-Hyun Kwon

Hong-Sik Kim

Sang-Gu Jo

Ki-Joong Kim

Hyun-Seok Kim

Yong-Kee Kwon

Kyung-min Lee

In-Hwa Jung

Jin Cheng

A memory system includes: an error correction code generation circuit suitable for generating an error correction code including one or more symbols for write data including a plurality of symbols, to output a codeword including the write data and the error correction code; a first data mapping circuit suitable for mapping the symbols of the codeword to a dataword; and a memory suitable for storing the dataword.

Memory system and memory module

A memory controller may be provided. A memory module may be provided. A memory system may be provided. A method of operating the memory system, the memory controller, or memory module may be provided. The memory system may include a memory controller and a memory module. The memory controller may provide data to the memory module to store data within the memory module. The memory controller may generate an index for storing the data. The index may be stored within the memory module.

Memory controller, memory module, and memory system and operation methods thereof

A memory controller includes a command input unit suitable for receiving a write command, a read command, and a send command, a command counting unit suitable for performing a counting operation in response to the write command to produce a counted data, a first Error Correction Code (ECC) encoding unit suitable for performing a first ECC encoding onto a data that is read from a memory device in response to the read command to produce a first ECC encoded data, a second ECC encoding unit suitable for performing a second ECC encoding onto the counted data in response to the send command to produce a second ECC encoded data, and a data output unit suitable for combining the first ECC encoded data and the second ECC encoded data to output a read data.

Memory controller, memory system including the same, and operation method thereof

Disclosed is a memory controller including a command decoder suitable for generating a data identifier of read data by decoding a read command, an update unit suitable for updating information of the read data in response to the data identifier of the read data, and a data output control unit suitable for storing data read from a memory device according to the read command, and selectively outputting the stored data as the read data based on the updated information.

A semiconductor device includes: a first memory chip including a plurality of first memory regions; a temporary memory chip including a plurality of temporary memory regions; and a control chip suitable for accessing a first access target memory region among the plurality of first memory regions or a first temporary memory region among the plurality of temporary memory regions based on first access information and first temperature readout information corresponding to the plurality of first memory regions.

Semiconductor device with temporary memory chip and method for driving the same

A memory device may include one or more multi-channel memories and an interface unit suitable for interfacing the multi-channel memories. The interface unit may include a first data interface suitable for transferring data for the first channel of the multi-channel memories, a second data interface suitable for transferring data for the second channel of the multi-channel memories, and an extra data interface suitable for transferring data for a selected one of the first channel and the second channel so that the data is additionally transmitted.

Memory device using extra read and write commands

A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.

Semiconductor system including replacement storage unit

A semiconductor memory device may include a memory cell array, and a program and verify circuit configured to perform a write operation on the memory cell array by repeating a plurality of program and verify operations. When the write operation is stopped after a first program operation is performed according to a first program condition, the PNV circuit may perform a first verify operation corresponding to the first program operation according to a first target value, after the write operation has resumed.

Semiconductor memory device, memory system including the same, and operating method thereof

A semiconductor device may include a candidate selector configured for generating a plurality of candidate threshold value sets from a plurality of digital values corresponding to a plurality of analog signals output from a memory cell array. The semiconductor device may include a threshold value selector configured for selecting one candidate threshold value set of the plurality of candidate threshold value sets as a threshold value set. The semiconductor device may include a comparator configured for deciding logic levels of the plurality of digital values according to the selected threshold value set.

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Seoul, South Korea

Young-Ook Song