Skhynix Inc.

Young Ock Hong

Byung Woo Kang

Hwal Pyo Kim

Jin Taek Park

Sae Jun Kwon

Seung Min Lee

Eun Seok Choi

Jae Taek Kim

Min Sung Ko

Seung Woo Han

Gwang Been Kim

Yang Seok Lim

There is provided a semiconductor device having a defect detection circuit. The semiconductor device includes a plurality of upper bonding pads, a plurality of lower bonding pads adhered to the plurality of upper bonding pads, a first upper line electrically connecting upper bonding pads, among the plurality of upper bonding pads, to each other; a plurality of lower lines electrically connected to the plurality of lower bonding pads; and a first defect detection circuit including an input terminal connected to a lower line, among the plurality of lower lines and an output terminal connected to another lower line, among the plurality of lower lines.

Semiconductor device having defect detection circuit

A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.

Method of planarizing insulating layer for memory device

A semiconductor device includes: a stack structure including a cell region and a contact region; a channel structure penetrating the cell region of the stack structure; trenches penetrating the contact region of the stack structure to different depths; and a stop structure penetrating the contact region of the stack structure, the stop structure being located between the trenches.

Semiconductor device and manufacturing method of semiconductor device

A semiconductor memory device includes: a stacked structure including first and second select patterns spaced apart from each other in a first direction; a gate isolation layer extending in a second direction intersecting the first direction between the first and second select patterns; channel structures penetrating the stack structure; and first and second bit lines extending in the first direction, the first and second bit lines being adjacent to each other. The channel structures include: a first channel structure which penetrates the first select pattern and is spaced apart by a first distance from the gate isolation layer in the first direction; and a second channel structure which penetrates the second select pattern and is spaced apart by substantially the first distance from the gate isolation layer in the first direction. The first and second channel structures are respectively connected to the second and first bit lines.

Semiconductor memory device

A semiconductor memory device includes a substrate including a peripheral circuit; an interconnection array disposed on the peripheral circuit; a cell stack structure disposed on the interconnection array, the cell stack structure including gate electrodes stacked in a vertical direction to form a cell step structure; and a dummy stack structure disposed on the interconnection array, the dummy stack structure including sacrificial layers stacked in the vertical direction to form a dummy step structure parallel to the cell step structure. The interconnection array includes a first lower conductive pattern including a center region overlapping with a slit between the cell step structure and the dummy step structure, a first region extending to overlap with the dummy step structure from the center region, and a second region extending to overlap with the cell step structure from the center region.

A semiconductor memory device includes a substrate including a peripheral circuit, a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction, a plurality of contact groups passing through the stepped dummy stack, and upper lines respectively connected to the contact groups. The contact groups include a first contact group having two or more first contact plugs arranged in the first direction. The upper lines include a first upper line commonly connected to the first contact plugs.

The present technology provides a semiconductor memory device. The semiconductor memory device includes a source film spaced from a substrate and disposed on the substrate, a conductive contact plug penetrating the source film, and a dummy stack body including dummy interlayer insulating films and sacrificial insulating films alternately stacked on the conductive contact plug.

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Icheon-si, South Korea

Young Ock Hong