Samsung Electronics Co., Ltd.

Young O Lee

Min Su Kim

Ah Reum Kim

Jeong Jin Lee

Doo Seok Yoon

Won Hyun Choi

The various embodiments of the present invention pertain to a method for operating a system for managing approval requests using email.

System for managing approval request using email and the operating method thereof

A pulse-based flip flop circuit includes a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving either a data signal or the scan input signal responsive to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes a direct path providing a clock signal as a direct path input to a NAND circuit; a delay path including a number of plural stages that delay the clock signal and provide a delayed clock signal as a delay path input to the NAND circuit that performs a NAND operation on the direct path and delay path inputs to generate the inverted pulse signal; and a feedback path providing the pulse signal to a first stage among the stages of the delay path.

Flip flop circuit

A semiconductor circuit and a layout system of the semiconductor circuit, the semiconductor circuit including a latch; a feedback inverter that receives an output signal of the latch via a first node and provides a feedback signal to the latch responsive to the output signal of the latch; and an output driver which receives the output signal of the latch via the first node and provides an output signal externally of the semiconductor circuit. The output driver includes an even number of inverters, and the latch, the feedback inverter, and the output driver share a single active region formed without isolation.

Semiconductor circuit and semiconductor circuit layout system

A semiconductor circuit and a semiconductor circuit layout system are provided. The semiconductor circuit includes a clock inverter which inverts a clock signal and outputs an inverted clock signal where the clock inverter is laid out between a second master latch main circuit configured to latch signals of a first node and a fourth node based on the clock signal and the inverted clock signal, respectively, and a second slave latch main circuit configured to latch signals of a second node and a fifth node based on the clock signal and the inverted clock signal, respectively.

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Seoul, South Korea

Young O Lee