International Business Machines Corporation

Young O Kim

Lars W Liebmann

Mark Alan Lavin

Ioana C Graur

Glenwood S Weinert

Carlos A Fonseca

Daniel Nelson Maynard

Alfred K Wong

Robert T Sayah

William F Pokorny

Philip J Russell

Donald G Chesebro

A method of designing an alternating phase shifting mask for projecting an image of an integrated circuit design. Phase units are binary colorable within each unit of the hierarchical circuit design, e.g., cell, an array, a net, or array of nets and/or cells, the phase shapes. The assignment of phases or colors within a hierarchical unit will be correctly binary colored to satisfy the lithographic, manufacturability and other design rules, referred to collectively as coloring rules. During assembly with other units, the coloring of phases in a hierarchical unit may change (e.g., be reversed or flipped), but the correct binary colorability of a hierarchical unit is preserved, which simplifies assembly of the integrated circuit layout.

System for coloring a partially colored design in an alternating phase shift mask

A method and computer program product is described for optimizing the design of a circuit layout that assigns binary properties to the design elements according to a hierarchy of rules. For example, the design of an alternating phase shifted mask (altPSM) is optimized first according to rules that assign phase shapes that maximize image quality for critical circuit elements, and then further optimized to minimize mask manufacturability problems without significantly increasing the complexity of the design process flow. Further optimization of the design according to additional rules can be performed in a sequentially decreasing priority order. As the priority of rules decrease, some violation of lower priority rules may be acceptable, as long as higher priority rules are not violated.

Priority coloring for VLSI designs

The method for selecting hierarchical interaction in a hierarchical shapes processor increases the operator's access and control over the handling of the design's hierarchical structure. The shapes of each cell are considered in accordance with a specified hierarchical relationship having constraints defined by the chosen mode of shape processing. The hierarchical relationships provide additional shape processing modes depending on the operator's physical design requirements.

Method for selecting hierarchical interactions in a hierarchical shapes processor

According to the preferred embodiment, a method is provided for automatically coloring VLSI design elements for the purpose of assigning binary properties to the elements. The preferred method is particularly applicable for use generating phase shift mask designs from VLSI CAD datasets. The preferred method uses net coloring to automatically generate a data set of colored elements. The preferred method is not dependent on the order in which the elements are operated upon. The preferred method has the additional advantage of being able to automatically detect conflicts that prevent the VLSI design from being optimally colored. The preferred method is equally applicable to hierarchical VLSI databases with nested components and traditional flat databases. When applied the hierarchical databases, the preferred method provides element coloring with minimal data flattening required.

Automatic generation of phase shift masks using net coloring

A process for creating and verifying a design of phase-shifted masks utilizing at least one phase shift region employing a computer-aided design system. A chip design is provided. A phase-shift mask design capable of producing the chip design is created. Features in a design of the phase-shifted mask that require phase shifting are located. Uncolored phase regions are created on opposite sides of the features. Proper phase termination of the phase regions is ensured based upon space constraints of a phase-shifted mask technique utilized. Phases are determined for the phase regions. Whether coloring errors and un-phase-shiftable design features exist is determined. Mask process specific overlaps and expansions are applied to the mask design to prepare designed data levels for mask manufacture. A residual phase edge image removal design is derived.

Phase shifted mask design system, phase shifted mask and VLSI circuit

An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill shapes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill shapes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.

Efficient generation of fill shapes for chips and packages

A method of nested maximum space computation is used for the processing of shapes in design data for integrated circuits and printed circuit electronic packages. This method determines the complement of a design level without unnecessary flattening or denesting thereby reducing the processing time and the volume of the output data. Native shapes are first expanded by one-half the maximum space ground rule value to get the expanded native shapes. The nested shape complementation method is applied to the expanded native shapes to get the error candidate shapes. The error candidate shapes indicate areas that are possible violations. Next, the expanded native shapes are subtracted from the error candidate shapes to get the real error shapes. The nested shape complementation method finds the regions between shapes in a hierarchical design without denesting. For each cell that does not have transforms of other cells, the nested shape complementation method finds the cell's proper frame and uses that frame and the cell's native shapes to create complemented shapes. For each cell with transforms of other cells, the nested shape complementation method finds the cell's proper frame and uses that frame, the cell's native shapes, and its transformed cell's frames to create complemented shapes. The complemented shapes are added to the cell as native shapes on a new design level.

Nested maximum space computation and efficient generation of nested

A computer-based system and method is provided for creating a representation of interconnections between VLSI circuit design components. A VLSI circuit design component identifying a leaf design entity is stored in memory. Placements in the design where the design component appears are stored in memory. A set of links is formed to connect placements to one another. The links further specify placement of the design component in the circuit design. The interconnections themselves are then computed. The interconnections denote where placements of the VLSI circuit design component instances are interconnected, and may specify any meaningful coupling, such as electrical conductivity, magnetic, or optical. The interconnections are represented by a nested net graph which includes a list of nets, and instance counts associated with the nets. The nested net graph may also include a second list, which specifies instances of lower nested nets contained in the nested net graph. The nested net graph may further include a shape-to-net table attached at the root of the nested net graph. The shape-to-net table defines a mapping from the VLSI circuit design component to a corresponding net. Also provided is a system and method for building interconnections using a bridge component, or bridge net. The bridge net denotes the interconnection between two nets derived from a pair of VLSI circuit design component instances.

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San Jose, CA, United States of America

Young O Kim