Samsung Electronics Co., Ltd.

International Business Machines Corporation

Young Mook Oh

Jeong Yun Lee

Geum Jung Seong

Seung Soo Hong

Sang Hyun Lee

Seung Ju Park

Jung Hyun Kim

Gi Gwan Park

Yong Seok Lee

Dong Seok Lee

Hyun Ji Kim

Sung Woo Myung

Sang Duk Park

Bo Soon Kim

Yong Ho Jeon

Young Hoon Song

Seung Mo Ha

Sug Hyun Sung

Kyung Seok Min

Youngjin Choi

Hae Geon Jung

Hyung Goo Lee

Seong Jin Nam

Bok Young Lee

Mi Gyeong Gwon

Semiconductor devices are provided. A semiconductor device includes a channel region that protrudes from a substrate. The semiconductor device includes a gate line on the channel region. Moreover, the semiconductor device includes a gate isolation layer that is between a first portion of the gate line and a second portion of the gate line. The gate isolation layer is in contact with the gate line and includes a gap that is in the gate isolation layer. Related methods of manufacturing a semiconductor device are also provided.

Semiconductor devices having a gate isolation layer and methods of manufacturing the same

A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

Semiconductor device and method for fabricating the same

A semiconductor device is provided. The semiconductor device includes a substrate, a first base fin protruding from the substrate and extending in a first direction, and a first fin type pattern protruding from the first base fin and extending in the first direction. The first base fin includes a first sidewall and a second sidewall, the first and second sidewalls extending in the first direction, the first sidewall opposite to the second sidewall, the first sidewall of the first base fin at least partially defines a first deep trench, the second sidewall of the first base fin at least partially defines a second deep trench, and a depth of the first deep trench is greater than a depth of the second deep trench.

Semiconductor device

A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a field insulating layer on the substrate, the field insulating layer wrapping a side wall of the fin type pattern, a gate electrode on the fin type pattern, the gate electrode extending in a second direction intersecting with the first direction, a first spacer on a side wall of a lower part of the gate electrode, and an etching stop layer extending along a side wall and an upper surface of an upper part of the gate electrode, along a side wall of the first spacer, and along an upper surface of the field insulating layer.

There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.

Semiconductor device and fabricating method thereof

Semiconductor devices are provided. The semiconductor device includes a first fin and a second fin on a substrate and a field insulation layer between the first fin and the second fin. The field insulation layer include a first insulation layer and a second insulation layer on the first insulation layer and connected to the first insulation layer. The second insulation layer is wider than the first insulation layer. A ratio of a top width to a bottom width of each of the first fin and the second fin exceeds 0.5.

Semiconductor device having field insulation layer between two fins

Methods of forming dual-damascene metal interconnect structures include forming an electrically insulating layer on an integrated circuit substrate and then forming a hard mask layer on the electrically insulating layer. The hard mask layer may include a stacked composite of at least four electrically insulating material layers therein. The hard mask layer may also have separate trench and via patterns therein that are respectively defined by at least first and second ones of the electrically insulating material layers and at least third and fourth ones of the electrically insulating material layers.

Methods of forming dual-damascene metal interconnect structures using multi-layer hard masks

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Hwaseong-si, South Korea

Young Mook Oh