Samsung Electronics Co., Ltd.

Other

Seoul National University

Samsung Sds Co., Ltd.

Young-Min Shin

Jong-min Kim

Chan-Wook Baik

Jung-Ah Choi

Larry R Barnett

Gun-Ok Jung

Seong-Jong Ha

Yong-Wan Jin

Gun-sik Park

Yeon-Hee Kwon

Sun-Ah Kang

Jin-Ho Choo

Bo-Youn Kim

Jin-kyu So

Jeong-Seon Yi

Disclosed is a method for reducing noise. The method comprises decoding a bitstream encoded with a first codec, acquiring Quantization Parameter (QP) values determined in a process of encoding the bitstream with the first codec, detecting a frame with noise by using the QP values and inputting the frame with noise to a predefined noise filter.

Method of reducing noise of video signal

A two-dimensional circuit for a traveling-wave tube for millimeter and sub-millimeter electromagnetic waves synchronously interacts with an electron beam in a vacuum electronic microwave amplifier or oscillator. The circuit is a solid body having a length along the tube axis. The solid body has an electrically conductive top section and an electrically conductive bottom section. The top section is configured with a plurality of vertical vanes having a width and height and configured parallel to each other. The bottom section is similarly configured such that when the circuit is viewed in cross section along the length, the vanes on the bottom section are staggered with respect to the vanes on the top section. The top section and the bottom section are separated from each other to define a tunnel through the solid body along the length.

Traveling-wave tube 2D slow wave circuit

A mask used for a Lithographie, Galvanofomung, and Abformung (LIGA) process, a method for manufacturing the mask, and a method for manufacturing a microstructure using a LIGA process. The method for manufacturing the microstructure using the LIGA process contemplates forming a substrate for the microstructure, a plurality of photosensitive layers, each photosensitive layer having a plating hole and an aligning pinhole, and an aligning pin capable of being inserted into the aligning pinhole, with the aligning pinholes of the photosensitive layers being formed in corresponding positions, and repeating a process of stacking the photosensitive layer on the substrate for the microstructure and a process of forming a plating layer by plating the plating hole of the stacked photosensitive layer with a metal for a number of times corresponding to the number of the photosensitive layers, and when the photosensitive layers are stacked on the substrate for the structure, the photosensitive layers being aligned with one another by inserting the aligning pin into the aligning pinholes of all the photosensitive layers stacked on the substrate for the microstructure to penetrate all the photosensitive layers.

Mask used for LIGA process, method of manufacturing the mask, and method of manufacturing microstructure using LIGA process

Provided are a circuit and a method of detecting clock delay where the circuit to detect clock delay includes a delay detection circuit and a clock forwarding circuit, the delay detection circuit detects a delay between a predetermined output clock signal and an input clock signal, if the detected delays are identical to one another, the circuit generates an initial parameter corresponding to the delay and if the detected delays are not identical to one another, continuously detects the delay until the detected delays are identical to one another, and generates a reset control signal in response to a system reset signal or a predetermined internal reset signal; the clock forwarding circuit loads and unloads the input data in response to the initial parameter, the circuit to detect clock delay can automatically detect the clock delay necessary for setting the initial parameter of the clock forwarding circuit and reset a master circuit and an external circuit that interfaces with the master circuit, thus performing data transmission without any errors.

Circuit to detect clock delay and method thereof

For distributing a signal to loads in an area, the area is divided into a plurality of regions. A respective signal point is disposed in each region for providing the signal to a load in the region. A respective diffusion point is disposed between any two neighboring signal points. The signal is initially applied to a center point of the signal and diffusion points. The signal when received at a given signal or diffusion point is transmitted to any of the signal or diffusion points within a maximum distance from the given signal or diffusion point.

Point diffusion signal distribution with minimized power consumption and signal skew

A semiconductor integrated circuit device has a normal operation mode and a scan test operation mode, and includes a pulse generating circuit and a scan flip-flop circuit. The pulse generating circuit generates pulse signals synchronized with a clock signal in each of the normal and scan test operation modes. The scan flip-flop circuit latches data in response to the pulse signals from the pulse generating circuit signal in each of the normal and scan test operation modes.

Semiconductor integrated circuit device having scan flip-flop circuit

A semiconductor integrated circuit includes a boundary scan register and a plurality of local monitor circuits. The local monitor circuits are arranged individually about peripheral circuit regions of a semiconductor integrated circuit, being spaced from the boundary scan register, in order to measure and predict operation speeds in accordance with local on-chip process variations at a plurality of locations on the peripheral circuit regions. The operational speed of the semiconductor integrated circuit is determined by taking correlations into account between an overall signal delay time measured by the boundary scan register and local signal delay times measured by the respective local monitor circuits.

Semiconductor integrated circuit with local monitor circuits

A clock forwarding circuit automatically detects the delay in transmission of data between a master circuit such as a central processing unit and a slave circuit such as a semiconductor memory and forwards clocks corresponding to the delay. The master circuit includes a clock forwarding circuit which generates a clock signal. The slave circuit is coupled to the master circuit and generates a second clock signal which is synchronized with the first clock signal. The clock forwarding circuit receives the second clock signal, detects delay between the first and second clock signals and sets initial data load/unload parameters of the master circuit based on the detected delay. By forwarding clocks, the data transmission between the clocked circuits can be performed in faultless fashion independently of the delay.

Clock forwarding circuit with automatic clock delay detection and initial parameter setting features

A method for controlling display video data on an LCD panel having a display matrix of pixels arranged in rows and columns and having a delta structure, which includes the steps of displaying the video data in its original (unchanged) form during a first field of the video data, and displaying the video data in a modified form during a second field of the video data, with alternate (e.g., odd-numbered) lines of the video data being shifted one pixel towards a first (e.g., right) side of the display matrix. A control circuit for implementing this method generates first and second control signals for controlling the operation of a column driving circuit which drives the columns of pixels of the display matrix in the appropriate manner.

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Seoul, South Korea

Young-Min Shin