Samsung Electronics Co., Ltd.

Young-Man Ahn

Chong-sam Chung

Tae-Kyung Kim

Jong-bae Kim

Seung-Jin Seo

Seung-Man Shin

Hae-jung Suh

Jung-Kuk Lee

Byung-Se So

Hea-jung Suh

You-Keun Han

Sang-Seok Kang

Byung-in Ma

Jin-Kyung Lee

Seok-Il Kim

Dan-Kyu Kang

Jong-Cheol Seo

In-sik Park

Du-seop Yoon

Tatsuhiro Otsuka

Hoe-Ju Chung

Byoung-ho Choi

Seok-jung Kim

Young-Jun Park

Sung-joo Park

Hui-chong Shin

Myung-Hee Sung

Kwan-joon Kim

Chil-Nam Yoon

Ho-Suk Lee

Young-Sun Jeon

Soon-Deok Jang

Jin-kyung Lee

Jun-Hee Shin

Sang-Jhun Hwang

Seung-Hee Mun

Jang-Hoon Yoo

Soo-Han Park

Yong-Han Yoon

A memory module is provided. A plurality of DRAMs is mounted on a PCB. At least one DRAM has an operating parameter different from other DRAMs according to a position where the at least one DRAM is mounted on the PCB.

Memory device, memory module including the memory device, method of fabricating the memory module, and method of repairing the memory module

A memory module having an address mirroring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (MRS) command during a rank-merged test mode. The register sets address signals, which are symmetrically connected to the first and second memory chips through through-via-holes (TVHs) or blind-via-holes (BVHs) of a printed circuit board, to be selectively mirrored.

Memory module having address mirroring function

A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory device includes at least one MRS input pad, at least one data input pad, and an operation mode determining circuit. The operation mode determining circuit generates an operation mode determining signal, when an MRS command input through the MRS input pad corresponds to a predetermined MRS command and data signals input through the data input pad or pads include a predetermined combination. Accordingly, the efficiency in the manufacturing and producing processes may be improved by determining the operation mode of the semiconductor memory device in a module assembly process.

Determining operation mode for semiconductor memory device

A multi-mode electrostatic discharge (ESD) circuit for a semiconductor chip comprises first and second ESD diodes. In a first mode, a body voltage greater than a power source voltage of the semiconductor chip is applied to the first ESD diode and a body voltage less than a ground voltage of the semiconductor chip is applied to the second ESD diode. In a second mode, a body voltage substantially equal to the power source voltage of the semiconductor chip is applied to the body of the first ESD diode and a body voltage substantially equal to the ground voltage of the semiconductor chip is applied to the second ESD diode.

Electrostatic discharge circuit and method for reducing input capacitance of semiconductor chip including same

A memory module includes a first memory group including a plurality of memory devices, a second memory group including a less number of memory devices with respect to the memory devices in the first memory group, a register configured to provide a command/address signal to the first memory group and a delayed command/address signal to the second memory group, a first signal line configured to transfer the command/address signal to the first memory group, and a second signal line configured to transfer the delayed command/address signal to the second memory group.

Memory module and register with minimized routing path

A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.

Memory module, memory unit, and hub with non-periodic clock and methods of using the same

A memory module test system including at least one memory module. The at least one memory module includes a first hub and a plurality of semiconductor memory devices. The system includes a tester for testing the at least one memory module. A second hub is located between the first hub and the tester. The second hub is for converting a memory command and memory data output from the tester into packet data and transmits the packet data to the first hub. The second hub converts the packet data output from the first hub into memory data and transmits the memory data to the tester.

Memory module test system for memory module including hub

A memory module testing apparatus and method include a test slot adapted to receive a target memory module, wherein the target memory module includes a first memory unit to store information related to the target memory module. The memory module testing apparatus further includes a second memory unit adapted to store information related to a memory module, and a first switching unit adapted to selectively provide a driving signal to at least one of the first memory unit and the second memory unit.

Memory module testing apparatus and method of testing memory modules

A semiconductor memory module and a semiconductor memory device are disclosed. In one embodiment, the invention provides a semiconductor memory module comprising a circuit board, a plurality of semiconductor memory devices adapted to operate during a test mode and a normal operation mode and mounted on the circuit board, a first signal line set comprising a plurality of first signal lines connected to the plurality of semiconductor memory devices, and a plurality of second signal line sets. Each semiconductor memory device comprises first terminals adapted to receive first signals from the first signal lines, second terminals connected to a corresponding one of the second signal line sets, a third terminal adapted to receive an enable signal during the test mode, and a signal transmitting unit adapted to output second signals to the second terminals in response to the enable signal.

Semiconductor memory module and semiconductor memory device

A compatible optical pickup compatibly using a high density recording medium and at least one low density recording medium, includes an objective lens to form a light spot suitable for use on a recording surface of the high density recording medium by focusing a corresponding incident light beam with a high NA suitable for the high density recording medium and a light spot suitable for use on another recording surface of the low density recording medium by focusing another corresponding incident light beam, and an actuator provided to apply tilt to the objective lens. The light beam for the low density recording medium is incident on the objective lens as a divergent beam. When the objective lens is shifted in a radial direction, a tilt is applied to the objective lens corresponding to the shift.

Compatible optical pickup applying tilt to objective lens in proportion to radial movement of objective lens

There is provided an output buffer circuit for a semiconductor memory device. The output buffer circuit includes: a main buffer and parallel connected auxiliary buffer receiving an input signal. A selection circuit controls the auxiliary buffer by selectively defining a selected input signal in relation to the input signal and an adjacent input signal.

Output buffer circuit for semiconductor memory device

A memory module and related method are disclosed. The memory module comprises a clock generator configured to generate first and second internal clock signals in relation to an external clock signal, and a register configured to receive the first and second internal clock signals. The register stores an external control/address signal in response to the first internal clock signal and transmits an internal control/address signal derived from the external control/address in response to the second internal control/address signal.

Memory system with registered memory module and control method

An optical pickup having a plurality of objective lenses. At least one of the plurality of objective lenses is configured so that a type of wavefront error mainly generated by a tilt of the at least one of the plurality of objective lenses is the same as a type of a wavefront error mainly generated by an angle at which light is incident upon the at least one of the plurality of objective lenses.

Lens correcting wavefront error caused by tilt and optical pickup using same

An optical disc apparatus and a wobble signal detection method in which a light beam projected onto an optical disc and reflected by the optical disc is divided into at least four light regions in the direction corresponding to the radial direction of the optical disc to detect the light regions, and a wobble signal is detected by performing a subtraction on first and second difference signals, the first difference signal obtained by performing a subtraction on detection signals for the inner light regions of the divided and/or detected light beam and the second difference signal obtained by performing a subtraction on detection signals for the outer light regions of the divided and/or detected light beam. Accordingly, when a wobble signal is reproduced from an optical disc manufactured by a wobble modulation manner, a wobble signal is prevented from being degraded due to the interference (cross talk) from the wobbles of adjacent tracks, even though the track pitch of the optical disc is reduced to improve the recording density.

Growing community of inventors

Gyeonggi-do, South Korea

Young-Man Ahn