Qualcomm Incorporated

The Boeing Company

Young Kyu Song

Kyu-Pyung Hwang

Dong Wook Kim

Xiaonan Zhang

Hong Bok We

Changhan Hobie Yun

Jong-Hoon Lee

Ryan David Lane

Uei-Ming Jow

Jonghae Kim

Daeik Daniel Kim

Sangjo Choi

Jung Ho Yoon

Mario Francisco Velez

Jae Sik Lee

Chengjie Zuo

Shiqun Gu

Aristotele Hadjichristos

Chin-Kwan Kim

Yunseo Park

Uei-ming Jow

John Jong-Hoon Lee

Terry R Vogler

Charles Muwonge

Babak Nejati

Victor Adrian Chiriac

Philipp Andreas Boettcher

Paragkumar Ajaybhai Thadesar

Steve Fanelli

Xiaoming Chen

Walid M Al-Bondak

Thomas D Mitchum

John Jong Hoon Lee

Thomas Gee

Uei Ming Jow

An assembly for electromagnetic interference (EMI) shielding to prevent incident radiation from penetrating through a gap to an interior of an aircraft includes an electromagnetic band gap (EBG) structure. The EBG structure has a patch-and-via array connected to a ground layer. The EMI shielding includes a conductive adhesive and is flexible for conforming attachment to curved aircraft surfaces. The shielding may be located on a deflector plate that is parallel to an adjacent aircraft surface, on the airframe surface opposite to the deflector plate, or in both locations. The assembly filters out penetrating electromagnetic energy and prevents highly resonant cavity mode build-ups of electromagnetic energy inside a nacelle or other enclosure effectively protecting electrical equipment in the interior.

RF filter device for aircraft nacelle access door gap

An electrical module assembly is provided. The electrical module assembly includes a circuit board with a first circuit-board surface and a second circuit-board surface defining a cavity, and an antenna disposed on the first circuit-board surface. The electrical module assembly also includes a wafer-level packaged (WLP) die embedded in the cavity. The WLP die has a first WLP die surface and a second WLP die surface. The second WLP die surface has electrical contacts thereon. The circuit board includes vias that extend from the antenna through the circuit board to the first WLP die surface to interconnect the antenna and the WLP die. The electrical module assembly further includes a second circuit board coupled to the second circuit-board surface, and coupled to the WLP die at the electrical contacts on the second WLP die surface of the WLP die.

Electrical module assembly with embedded dies

A method for modeling electromagnetic characteristics of a vehicle having electrical components comprising generating a parallel plate waveguide model and inserting a vehicle model for the vehicle within the parallel plate waveguide model. The vehicle model has a plurality of lumped ports corresponding to on-board electrical components. The method executes an electromagnetic field solver on a first and second waveguide ports and the lumped ports and determines a scaling factor between a first power level configured to excite the first and/or second waveguide ports and a second power level configured to excite the lumped ports. The electromagnetic field solver runs on the first and second waveguide and lumped ports, producing a first output data and the method produces a scattering parameter (S-parameter) model for the vehicle from the first output data that includes a plurality of S-parameter ports.

Method for high-intensity radiated field (HIRF) and electromagnetic pulse (EMP) analysis of a vehicle

A fire suppressing device including a torus container with a main body defining an interior chamber and a discharge port, the interior chamber configured to receive and retain metal organic framework materials. The fire suppressing device also includes an inductor coil extending through the interior chamber of the torus container and surrounding the metal organic framework materials. The inductor coil is configured to heat the metal organic framework materials to form a fire suppressing substance that is conveyed through the discharge port.

Fire suppressing device

In one or more embodiments, a method of manufacturing a high impedance surface (HIS) apparatus comprises patterning a first conducting layer on a core to form a first set of conducting pads, and patterning a second conducting layer on the core to form a second set of conducting pads. The method further comprises applying solder paste to each of the conducting pads of the second set of conducting pads. Also, the method comprises placing chip capacitors on the solder paste on the second set of conducting pads. In addition, the method comprises applying underfill between the chip capacitors. Also, the method comprises applying solder paste to each of the conducting pads of the first set of conducting pads. In addition, the method comprises placing chip inductors on the solder paste on the first set of conducting pads. Further, the method comprises applying underfill between the chip inductors.

Methods of manufacturing a high impedance surface (HIS) enhanced by discrete passives

In one or more embodiments, a high impedance surface (HIS) apparatus comprises a core; a first set of conducting pads, where a first side of the first set of conducting pads is connected to a first side of the core; and a second set of conducting pads, where a first side of the second set of conducting pads is connected to a second side of the core. The apparatus further comprises a plurality of chip inductors, where at least a portion of the chip inductors are connected to a second side of the first set of conducting pads; and a plurality of chip capacitors, where at least a portion of the chip capacitors are connected to a second side of the second set of conducting pads.

High impedance surface (HIS) enhanced by discrete passives

A resistor assembly is disclosed and comprises a first conductive trace, a second conductive trace, and a plurality of trimming bridges that electrically couple the first conductive trace to the second conductive trace. The resistor assembly also comprises a thin film resistor electrically coupled to the first conductive trace. The first conductive trace, the second conductive trace, the plurality of trimming bridges, and the thin film resistor are all part of a surface mounted layer of the resistor assembly. The plurality of trimming bridges are each removable to increase a resistance of the thin film resistor.

Thin film resistor having surface mounted trimming bridges for incrementally tuning resistance

A variable RF attenuator includes a substrate, a first microstrip trace, a first thin film resistor, a second microstrip trace, and a wire bond. The substrate includes a dielectric layer. The first thin film resistor is disposed on the substrate. The first microstrip trace is disposed on the substrate and the first thin film resistor. The second microstrip trace is disposed on the substrate and is uncoupled from the first microstrip trace. The wire bond extends from the second microstrip trace to a position on the first microstrip trace. The position is selected to tune RF attenuation over a conductive path defined by the first microstrip trace, the wire bond, and the second microstrip trace.

Variable radio frequency attenuator

Some features pertain to a device package that includes a die and a package substrate. The die includes a first switch. The package substrate is coupled to the die. The package substrate includes at least one dielectric layer, a primary inductor, and a first secondary inductor coupled to the first switch of the die. The first secondary inductor and the first switch are coupled to a plurality of interconnects configured to provide an electrical path for a reference ground signal. The primary inductor is configurable to have different inductances by opening and closing the first switch coupled to the first secondary inductor. In some implementations, the primary inductor is configurable in real time while the die is operational. In some implementations, the die further includes a second switch, and the package substrate further includes a second secondary inductor coupled to the second switch of the die.

Integrated device package comprising a real time tunable inductor implemented in a package substrate

A resistor assembly is disclosed and comprises a surface mounted layer comprising a first conductive trace, a second conductive trace, and a plurality of trimming bridges that electrically couple the first conductive trace to the second conductive trace. The resistor assembly also comprises a second layer disposed underneath the surface mounted layer. The second layer comprises an embedded thin film resistor electrically coupled to the surface mounted layer. The plurality of trimming bridges are each removable to increase a resistance of the embedded thin film resistor. The resistor assembly also comprises a plurality of vias that electrically couple the first conductive trace of the surface mounted layer to the embedded thin film resistor.

Some features pertain to a package substrate that includes at least one dielectric layer, an inductor in the at least one dielectric layer, a first terminal coupled to the inductor, a second terminal coupled to the inductor, and a third terminal coupled to the inductor. The first terminal is configured to be a first port for the inductor. The second terminal is configured to be a second port for the inductor. The third terminal is a dummy terminal. In some implementations, the package substrate includes a solder resist layer over the dielectric layer, where the solder resist layer covers the third terminal. In some implementations, the package substrate includes a solder interconnect over the third terminal, such that the solder resist layer is between the third terminal and the solder interconnect. In some implementations, the package substrate is coupled to a die comprising a plurality of switches.

Integrated device package comprising a tunable inductor

An integrated radio frequency (RF) circuit structure may include a resistive substrate material and a switch. The switch may be arranged in a silicon on insulator (SOI) layer supported by the resistive substrate material. The integrated RF circuit structure may also include an isolation layer coupled to the SOI layer. The integrated RF circuit structure may further include a filter, composed of inductors and capacitors. The filter may be arranged on a surface of the integrated RF circuit structure, opposite the resistive substrate material. In addition, the switch may be arranged on a first surface of the isolation layer.

Monolithic integration of antenna switch and diplexer

Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

Integrated circuit package comprising surface capacitor and ground plane

A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.

Patterned grounds and methods of forming the same

A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

Growing community of inventors

San Diego, CA, United States of America

Young Kyu Song