Samsung Electronics Co., Ltd.

Young-Kwang Yoo

Young-Jin Cho

Jae-Geun Park

Soon-Suk Hwang

Young-Sik Kim

Eun-chu Oh

Jeong-ho Lee

Young-geun Lee

A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

Memory system with multiple channel interfaces and method of operating same

A memory controller configured to control a memory device including a plurality of banks. The memory controller may determine whether a number of write commands enqueued in a command queue of the memory controller exceeds a reference value, calculate a level of write power to be consumed by the memory device in response to at least some of the write commands from among the enqueued write commands when the number of enqueued write commands exceeds the reference value, and schedule, based on the calculated level of write power, interleaving commands executing an interleaving operation of the memory device, from among the enqueued write commands.

Memory controller and operating method thereof

Growing community of inventors

Yongin-si, South Korea

Young-Kwang Yoo