Samsung Electro-mechanics Co., Ltd.

Sungkyunkwan University

Samsung Electronics Co., Ltd.

Toray Saehan Incorporated

Young Kwan Lee

Seung Eun Lee

Young Sik Hur

Yong Hoon Kim

Hak Chun Kim

Jae Do Nam

Mi Suk Cho

Myung Sam Kang

Won Wook So

Yun Tae Lee

Jung Hyun Cho

Won Jae Joo

Hyouk Ryeol Choi

Ho Kwon Yoon

Byung Hee Sohn

Kwi Jong Lee

Ja Choon Koo

Kyoung Jun Kim

Yi Yoiung Yun

Seung Ryong Kook

Seung Yeop Kook

Joo Hwan Jung

Su Jin Lee

Kyung Hwan Ko

Ju Hee Park

Baek Chul Kim

Jeong Cho

Choong Nam Park

Hyung Pil Moon

Hye In Kim

Chang Kyung Woo

Jin Ah Chung

Je Kyoung Kim

Su Jeong Lee

Chang Kyu Lee

Young Seop Kim

Jong Rok Kim

Sung Gi Kim

A bridge embedded interposer and a package substrate and a semiconductor package including the same includes: a connection structure including one or more redistribution layers, a first bridge disposed on the connection structure and including one or more first circuit layers electrically connected to the one or more redistribution layers, a frame disposed around the first bridge on the connection structure and including one or more wiring layers electrically connected to the one or more redistribution layers, and an encapsulant disposed on the connection structure and covering at least a portion of each of the first bridge and the frame.

Bridge embedded interposer, and package substrate and semiconductor package comprising the same

An electronic component-embedded substrate includes an electronic component module having a first surface and a second surface opposite to the first surface, and including a first support member having a first through-portion, a first electronic component disposed in the first through-portion, a first resin layer covering at least a portion of the first electronic component, a second support member disposed on one side of the first support member and having a second through-portion, a second electronic component disposed in the second through-portion and connected to the first electronic component, and a second resin layer covering at least a portion of the second electronic component, an insulating material covering at least a portion of each of a side surface of the electronic component module and the first surface, and a first wiring layer disposed on the insulating material and connected to the first electronic component.

Electronic component-embedded substrate

A substrate-on-substrate structure and an electronic device including the same are provided. The substrate-on-substrate structure includes: a first printed circuit board having a first side and a second side; a second printed circuit board disposed on the second side of the first printed circuit board, and having a first side connected to the second side of the first printed circuit board and a second side opposite to the first side connected to the second side of the first printed circuit board; a reinforcing structure attached to the first side of the second printed circuit board, and spaced apart from the second side of the first printed circuit board; and an underfill resin disposed between the second side of the first printed circuit board and the first side of the second printed circuit board, and covering at least a portion of the reinforcing structure.

Substrate-on-substrate structure and electronic device comprising the same

A substrate-on-substrate structure and an electronic device including the same are provided, and the substrate-on-substrate structure includes: a first printed circuit board having a first side and a second side, opposite to the first side; a second printed circuit board disposed on the second side of the first printed circuit board, and having a first side connected to the second side of the first printed circuit board and a second side opposite to the first side connected to the second side of the first printed circuit board; a first structure disposed on the second side of the first printed circuit board, and disposed around the second printed circuit board; a second structure disposed on the second side of the second printed circuit board; and a third structure disposed on the first and second structures, and connected to each of the first and second structures.

Substrate on substrate structure and electronic device comprising the same

A semiconductor package includes: a core structure having first and second surfaces and having first and second through-holes; a first semiconductor chip embedded in the core structure and having first and second contacts disposed on two opposing surfaces thereof, respectively; a first wiring layer on the surface of the core structure and connected to the first contact; a second wiring layer on the second surface of the core structure and connected to the second contact; a chip antenna disposed in the first through-hole; a second semiconductor chip in the second through-hole and having a connection pad; a first redistribution layer on the first surface of the core structure and connected to the connection terminal, the connection pad, and the first wiring layer; an encapsulant encapsulating the chip antenna and the second semiconductor chip; and a second redistribution layer on the encapsulant connecting to the second wiring layer.

Semiconductor package

An electronic component embedded substrate includes a core layer having a first cavity and a second cavity on a first surface and a second surface of the core layer, respectively, the second surface opposite to the first surface in a thickness direction of the core layer; an electronic component disposed in the first cavity; a first insulating material covering at least a portion of the electronic component; a first wiring layer disposed on the first insulating material and connected to the electronic component; a built-in block disposed in the second cavity; and a second insulating material covering at least a portion of the built-in block.

Electronic component embedded substrate

A package-on-package includes a first semiconductor package including a first semiconductor chip and a second semiconductor package, disposed on the first semiconductor package, including a second semiconductor chip electrically connected to the first semiconductor chip. Each of the first and second semiconductor chips includes one or more units. The number of units of the first semiconductor chip is greater than the number of units of the second semiconductor chip. The one or more units of the first semiconductor chip and the one or more units of the second semiconductor chip implement a function of an application processor chip.

Package on package and package connection system comprising the same

A package-on-package and a package connection system including the same are provided. The package-on-package includes a first semiconductor package including a first semiconductor chip, and a second semiconductor package disposed on the first semiconductor package and including a second semiconductor chip electrically connected to the first semiconductor chip. The first semiconductor chip includes an application processor (AP) including a first image signal processor (ISP), and the second semiconductor chip includes a second image signal processor (ISP).

Package-on-package and package connection system comprising the same

There are provided a printed circuit board including: an insulation layer in which a via hole is formed; vias formed in the via hole; first circuit patterns formed below the insulation layer and electrically connected to the vias; and second circuit patterns formed on the insulation layer to be bonded to the vias; wherein the via has a diameter smaller than that of the via hole, and a method of manufacturing a printed circuit board.

Printed circuit board and method of manufacturing the same

Disclosed herein is a monomer for binding nano-metal, which is useful for the preparation of a conductor having increased conductivity with ensuring flexibility and transparency. Polymerization of the monomer for binding nano-metal provides a conductive polymer composite including a nano-metal rod. A method of preparing the conductive polymer composite is also provided.

Monomer for binding nano-metal, conductive polymer composite and method of preparing the conductive polymer composite

Disclosed herein are a coreless board for a semiconductor package and a method of manufacturing the same. The coreless board for the semiconductor package includes: a support; a build-up layer formed on the support; an external connection terminal formed on the build-up layer; and a solder resist layer formed on the build-up layer so as to expose the external connection terminal.

Coreless board for semiconductor package, method of manufacturing the same, and method of manufacturing semiconductor package using the same

Provided is a method of forming a uniform graphene layer on a substrate (metal- or conductive-polymer-coated, ITO) by doping expanded graphite using various kinds of dopants (Lewis acid) to grant a positive charge thereto, dispersing the doped expanded graphite in an organic solvent using ultrasonic waves to obtain a solution in which the graphene is dispersed in the organic solvent, and electrically applying a negative voltage to the solution.

Electrodeposition of graphene layer from doped graphite

A monomer for binding nano-metal, which is useful for the preparation of a conductor having increased conductivity with ensuring flexibility and transparency. Polymerization of the monomer for binding nano-metal provides a conductive polymer composite including a nano-metal rod. A method of preparing the conductive polymer composite is also provided.

There is provided a capacitor sensor capable of controlling sensitivity, wherein the capacitor sensor measures the magnitude and direction of a shear force applied to the sensor, as well as the magnitude of a normal force applied on the surface of the sensor, and consists of a single cell including a pattern electrode capable of varying its shape to control the sensitivity of the sensor.

Capacitor sensor capable of controlling sensitivity

Disclosed herein are a method for surface-treating a printed circuit board and a printed circuit board including a surface treatment layer. The method includes: plasma-treating a surface of a printed circuit board; treating the plasma-treated substrate with an organic solderability preserve; performing heat treatment on the substrate treated with the organic solderability preserve; printing a solder paste on the substrate subjected to the heat treatment; reflowing the solder paste printed substrate to fix the solder paste; and deflux washing the resulting substrate. According to the present invention, the discoloration problem due to oxidation of copper can be solved by performing heat treatment under predetermined conditions after treatment with an organic solderability preserve. Therefore, the present invention can meet various multi-reflow processes, as compared with products of the related art.

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Seoul, South Korea

Young Kwan Lee