Samsung Electronics Co., Ltd.

Young Kun Jee

Un-Byoung Kang

Jongho Lee

Sunkyoung Seo

Un Byoung Kang

Joonho Jun

Tae Hong Min

Ji Hwang Kim

Sangwon Kim

Minsoo Kim

Jung-Hwan Kim

Hyoungjoo Lee

Chajea Jo

Yun Seok Choi

Il Hwan Kim

Taeje Cho

Wonjae Lee

Jihwan Hwang

Kwang-Chul Choi

Teak Hoon Lee

Hae-Jung Yu

Dae-Woo Kim

Ii Hwan Kim

A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

Methods of inspection of semiconductor packages including measurement of alignment accuracy among semiconductor chips

Semiconductor packages

A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

Semiconductor package having redistribution layer

A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

Semiconductor package having dummy pads and method of manufacturing semiconductor package having dummy pads

Semiconductor packages including stacked substrates and penetration electrodes

A semiconductor chip module includes a chip package and a printed circuit board (PCB) to which the chip package is mounted. The chip package includes a substrate, a processor disposed in a central region of the substrate, a plurality of active chips disposed around the processor, a plurality of dummy chips disposed in spaces between the plurality of active chips, and an epoxy resin fixing the plurality of active chips and the plurality of dummy chips to the substrate. Channels of the epoxy resin extend between an uppermost surface of a chip body of each of the dummy chips and the substrate of the chip package to control or mitigate warping of the chip package.

Semiconductor chip module including a channel for controlling warpage and method of manufacturing the same

A semiconductor package includes a first semiconductor chip stacked on a package substrate in which a first surface of the first semiconductor chip faces the package substrate and a second surface that is opposite to the first surface, a second semiconductor chip stacked on the first semiconductor chip that includes a third surface facing the first semiconductor chip and a fourth surface that is opposite to the third surface, and an integral adhesive structure that substantially continuously fills a first space between the package substrate and the first semiconductor chip and a second space between the first and second semiconductor chips. The integral adhesive structure includes an extension protruding from outer sidewalls of the first and second semiconductor chips. The extension has one continuously convex sidewall between a level of the first surface and a level of the fourth surface.

Semiconductor package and method for fabricating the same

Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

Semiconductor packages and methods of manufacturing the same

A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.

Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same

Growing community of inventors

Cheonan-si, South Korea

Young Kun Jee