Samsung Electronics Co., Ltd.

Young-kuk Kim

Yong-jin Kim

Min-chul Kim

In-seak Hwang

Jae-il Jung

Jin-hyoung An

Sung-rae Cho

Han-jin Lim

Ki-Vin Im

Dong-Ho Ahn

Sung-min Yoon

Mi-lim Park

Bo-un Yoon

Hideki Horii

Young-wook Park

Byoung-Deog Choi

Doo-Hwan Park

Gyu-Hwan Oh

Byoung-ho Kwon

Hyun-jung Lee

Jeon-Il Lee

Man-Sug Kang

Dong-Seok Suh

Jin-ho Oh

Mi-Lim Park

Young-ho Koh

Yang-hee Lee

Hori Ihideki

An electronic apparatus for acquiring a panorama image using a plurality of cameras and a method for controlling the electronic apparatus thereof are provided. The electronic apparatus includes a plurality of cameras for capturing an image, a sensor for acquiring movement information, and a processor for determining individual movement information of the plurality of cameras with reference to a predefined location using movement information acquired through the sensor, acquiring a plurality of images through the plurality of cameras based on the individual movement information and generating a panorama image using the plurality of photographed images.

Electronic apparatus and method for controlling electronic apparatus thereof

An electronic apparatus for providing a panorama image and a controlling method thereof are provided. The method includes acquiring photograph setting values of first images photographed respectively through a plurality of cameras, resetting a photograph setting value to be applied to at least one of the plurality of cameras based on the acquired photograph setting values and generating a panorama image comprising second images photographed through the plurality of cameras using the reset photograph setting value.

Electronic apparatus for providing panorama image and control method thereof

A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.

Semiconductor device and method of manufacturing the same

Active patterns spaced apart from each other by an isolation layer are formed in a substrate. Gate structures extending in the isolation layer through the active patterns are formed. Each active pattern is divided into a central portion and a peripheral portion facing the central portion by the gate structures. A protrusion of at least one of active pattern is formed. The protrusion is exposed from a top surface of the isolation layer, and transformed into silicide such that a first silicide ohmic pad is formed at the central portion of the active pattern and a second silicide ohmic pad is formed at the peripheral portion of the active pattern. A conductive line structure electrically connected to the first silicide ohmic pad is formed. A conductive contact electrically connected to the second silicide ohmic pad is formed. A data storage unit electrically connected to the conductive contact is formed.

Methods of manufacturing semiconductor devices

A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.

Semiconductor devices having self-aligned contact pads

A non-volatile memory device includes a data storage structure coupled between first and second conductive lines of the memory device. The data storage structure includes a conductive lower heater element, a data storage pattern, and a conductive upper heater element sequentially stacked. At least one sidewall surface of the data storage pattern is coplanar with a sidewall surface of the upper heater element thereabove and a sidewall surface of the lower heater element therebelow. Related fabrication methods are also discussed.

Non-volatile memory devices having dual heater configurations and methods of fabricating the same

Methods of manufacturing semiconductor devices having self-aligned contact pads

Methods of manufacturing non-volatile memory devices may include separating first phase-change material groups and second phase-change material groups, which have different sizes, from a target including phase-change materials and faulting a phase-change material layer on an object by using the first phase-change material groups and the second phase-change material groups.

Methods of manufacturing non-volatile phase-change memory devices

An apparatus and method for managing the layout of a window is provided. The apparatus includes a display unit that displays the window on a screen; the screen is divided into a plurality of display areas; a pointer-position-checking unit that checks the coordinate position of a pointer moved by a user and determines the one display area corresponding to the position of the checked pointer; and a window-size-adjusting unit that moves the window to the one display area where the pointer is positioned and adjusts the size of the window in proportion to the size of the one display area.

Apparatus and method for managing layout of a window

A probe card and a test apparatus including the probe card for improving test reliability. The probe card may include a first input terminal Microelectromechanical Systems (MEMS) switch that connects a first input terminal and a first input probe pin, wherein the first input terminal MEMS switch comprises a control portion that receives an operation signal and a connection portion that connects the first input terminal and the first input probe pin. The probe card may further include a first output terminal MEMS switch that connects a first output terminal and a first output probe pin, wherein the first output terminal MEMS switch comprises a control portion that receives the operation signal and a connection portion that connects the first output terminal and the first output probe pin.

Probe card and test apparatus including the same

A method of measuring a resistance of a memory cell in a resistive memory device can be provided by applying a data write pulse to a selected cell of the resistive memory device, applying a resistance read pulse to the selected cell after a delay time measured from a time of applying the data write pulse, measuring a drop voltage at the cell responsive to a pulse waveform output when applying the resistance read pulse to the selected cell, measuring a total current through the cell using the drop voltage and an internal resistance of a test device coupled to the cell, and determining a resistance of the resistive memory device using the total current and a voltage of the resistance read pulse.

Method of measuring a resistance of a resistive memory device

Phase change memory devices may be fabricated by forming a first electrode on a substrate and forming a chalcogenide material on the first electrode. The chalcogenide material is plasma treated sufficiently to induce a plasma species throughout the chalcogenide material. A second electrode is formed on the chalcogenide material. Related devices are also described.

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Seoul, South Korea

Young-kuk Kim