Samsung Electronics Co., Ltd.

Young-Kug Moon

Jong-Soo Seo

Woo-Yeong Cho

Kwang-Jin Lee

Byung-Gil Choi

Won-Seok Lee

Kwang-Ho Kim

Hye-Jin Kim

In-gyu Baek

Hong-Sun Hwang

Hak-soo Yu

Jun-Soo Bae

Joon-Min Park

Bo-Tak Lim

Su-Yeon Kim

Ik-chul Kim

A memory device includes a plurality of memory chips, including one or more memory chips that store authentication information, and a controller including a first register that stores information indicating a representative memory chip, from among the one or more memory chips that store the authentication information, that stores valid authentication information.

Memory device comprising a plurality of memory chips, authentication system and authentication method thereof

A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers.

Semiconductor memory device

A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs the received data, and a page mode setting unit that sets one of a first page mode and a second page mode as a page mode. In the first page mode, the data output unit sequentially reads the read data prefetched in the data register as page addresses are sequentially received, and in the second page mode, the data output unit sequentially reads the read data prefetched in the data register after a start page address among a plurality of page addresses has been received.

Resistance variable memory device

A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.

Variable resistance memory device and system thereof

A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations.

Resistance-change random access memory device including memory cells connected to discharge elements

A phase-change random access memory (PRAM) device includes a PRAM cell array including a first sector and a second sector, a first global bit line coupled to a first local bit line of the first sector and a first local bit line of the second sector, and a first plurality of global bit line discharge units coupled to the first global bit line, the first plurality of global bit line discharge units configured to discharge the first global bit line in response to a first global discharge signal.

Phase-change random access memory device, system having the same, and associated methods

A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transistors selectively connecting the global bit line with each of the plurality of local bit lines. Each column select transistor has a resistance that depends on distance from the write circuit and the read circuit.

Phase change random access memory device

A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.

Growing community of inventors

Suwon-si, South Korea

Young-Kug Moon