Skhynix Inc.

Hynix Semiconductor Inc.

Young-Jun Yoon

Kang-Sub Kwak

Joon-Yong Choi

Byung-Deuk Jeon

Dong-Geum Kang

Hyun-Seung Kim

Sang-Sic Yoon

Ki-Up Kim

A semiconductor memory device includes a memory region including a plurality of memory blocks, and suitable for outputting first and second read data from first and second memory blocks among the plurality of memory blocks based on first and second read control signals and a read address signal; a scheduler suitable for outputting a read scheduling signal based on the first and second read control signals; and an output driver suitable for outputting the first and second read data by a predetermined burst length alternately twice or more to a data pad based on a mode signal, wherein the first read data are outputted to the data pad according to a first burst sequence, and the second read data are outputted to the data pad according to a second burst sequence, based on the read scheduling signal.

Semiconductor memory device and operating method thereof

A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Memory system and operating method thereof

A memory system comprises: a memory cell array suitable for storing first data and a first parity, which is used to correct an error of the first data; and an error correcting circuit suitable for generating second data and a second parity, which includes bits obtained by correcting an error of the first parity and a bit obtained by correcting an error of a second sub-parity; wherein the error correcting circuit includes: a single error correction and double error detection (SECDED) parity generator suitable for generating a second pre-parity, which includes a first sub-parity and the second sub-parity; a syndrome decoder suitable for generating a first parity error flag and a first data error flag by decoding a syndrome; a SEC parity corrector suitable for correcting an error of the first parity based on the first parity error flag; a DED parity error detector suitable for generating a second sub-parity error flag based on an error information of the first data used to generate the second sub-parity; and a DED parity corrector suitable for correcting any error of the second sub-parity based on the second sub-parity error flag.

Memory system and operating method of the memory system

An operating method for a semiconductor memory device includes: generating a whole-domain-crossing-unit reset signal based on a domain-crossing-unit reset signal input to a whole-domain-crossing-unit-reset-signal generator; and resetting a counter synchronized to a data clock of a domain-crossing unit based on the whole-domain-crossing-unit reset signal during a data clock preparation section in which the data clock does not toggle.

Semiconductor memory device for resetting counter synchronized with data clock by using reset signal synchronized with system clock and method for operating the same

A semiconductor system may include first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad.

Semiconductor system

A semiconductor device includes a driving unit suitable for driving a plurality of signal lines, which are directly coupled to a plurality of bump pads, to a preset voltage level in a level determination period, and adjusting the preset voltage level in a predetermined order when the level determination period is repeated, a signal input circuit suitable for receiving voltage levels that are inputted through the signal lines and determining logic values for the inputted voltage levels of the signal lines, and an operation unit suitable for receiving voltage levels of the signal lines from the signal input circuit in a parallel manner in the level determination period, latching the logic values of the voltage levels, and serially outputting the logic values through a probe pad.

Semiconductor device and operation method thereof

A semiconductor system may include a first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad.

A semiconductor memory device includes a plurality of first pads and a plurality of memory unit blocks. The plurality of first pads are configured to input/output data in a test mode. The plurality of memory unit blocks each include a plurality of second pads configured to input/output data in a normal mode, and a plurality of data path selection units configured to connect internal circuits of the corresponding memory unit block to the plurality of first pads or the plurality of second pads in response to a unit block selection flag signal, a write enable signal, a read enable signal, and a mode control signal.

Semiconductor memory device and test method thereof

A semiconductor integrated circuit includes a bump pad through which data is outputted, a probe test pad having a larger size than the bump pad, a first output drive unit configured to drive the bump pad at a first drivability in response to output data, a second output drive unit configured to drive the probe test pad at a second drivability higher than the first drivability in response to the output data, and a multiplexing unit configured to transfer the output data to the first output drive unit or the second output drive unit in response to a test mode signal.

Semiconductor integrated circuit

A data output circuit for a semiconductor memory device includes a first driver configured to output a first drive control signal in response to a data signal, a drive controller configured to compare a voltage level of the first drive control signal with a reference voltage and output a second drive control signal, and a second driver configured to drive an output terminal in response to the first drive control signal and additionally drive the output terminal in response to the second drive control signal.

Data output circuit for semiconductor memory device

A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

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Gyeonggi-do, South Korea

Young-Jun Yoon