Samsung Electronics Co., Ltd.

Young-Jun Kwon

Jae-hong Park

Jun-whan Ahn

Ki-Young Choi

Hyeok-Man Kwon

Deum-Ji Woo

Yong Je Lee

Sun-gyeum Kim

Sang-hoon Lee

Nak-hee Seong

Tae-Sun Kim

Jung-rae Kim

Jin-Pyo Park

Seon-Young Yeo

A multi-bus system includes a first layer bus, a second layer bus connected to the first layer bus, at least one master device, and a decoder. The at least one master device is configured to be connected to the first layer bus via a first data path, and configured to be connected to the second layer bus via a second data path. The decoder is configured to directly connect the at least one master device to the first layer bus via the first data path, and directly connect the at least one master device to the second layer bus via the second data path.

Multi-bus system

In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Semiconductor memory device including non-volatile memory, cache memory, and computer system

A system on chip (SoC) includes a system bus; a plurality of intellectual properties (IPs) outputting bus signals via the system bus; and one or more checkers disposed to correspond to at least some of the plurality of IPs, wherein the checker includes: a first environment setting register for setting information about a check target and list, on which a bus protocol check operation will be performed, wherein the setting may be variable according to an access from outside via the system bus; and a check logic receiving the bus signal and performing a bus protocol check operation on a signal included in the bus signal according to the information set in the first environment setting register.

Bus protocol checker, system on chip including the same, bus protocol checking method

An image data compression system, for compressing a frame represented as a plurality of blocks, can include: a lossless compression unit to receive the plurality of blocks and to perform lossless compression thereon resulting in a first code; a lossy compression unit to receive the plurality of blocks and to perform lossy compression thereon resulting in a second code; and a code selection circuit to selectively output one of the first and second codes based upon a figure of merit evaluated for at least one of the first and second codes.

Hybrid image data processing system and method

A video decoder organizes and stores pixel lines of a reference picture into first and second memory devices. The video decoder then reads portions of a pixel block from the first and second memory devices and processes such a pixel block for generating a subsequent picture. By reading from the first and second memory device with time overlap, latency is minimized for faster video decoding.

Method and apparatus for decoding video data

A developing cartridge and an image forming apparatus utilizing the developing cartridge are provided. The developing cartridge includes a frame, a photosensitive drum which is rotatably installed upon the frame, a developing unit for developing an electrostatic latent image formed on the outer surface of the photosensitive drum, and a transfer unit having a brush with fibers for transferring a toner image from the outer surface of the photosensitive drum onto paper, a voltage unit for selectively applying a predetermined positive or negative voltage to the brush, and a rotary unit for enabling the fibers of the brush to engage the outer surface of the photosensitive drum after the developing cartridge is fully installed within the image forming apparatus.

Growing community of inventors

Seongnam-si, South Korea

Young-Jun Kwon