Hynix Semiconductor Inc.

Skhynix Inc.

Young-Jun Ku

Ki-Ho Kim

Ji-Eun Jang

Tae-Sik Yun

Jeong-Yoon Ahn

Hoon Moo Choi

Beom-Ju Shin

Seok-Cheol Yoon

Jae-Bum Ko

Kyoung-Nam Kim

Jong-Chern Lee

Kee-Teok Park

Dae-Suk Kim

kang-Seol Lee

Min-Su Park

Jang-Ryul Kim

A semiconductor device includes a mode control circuit suitable for selectively masking first and second initial input control signals and an initial feedback signal depending on a mode control signal and outputting first and second input control signals and a feedback signal; and a multiple-input shift register (MISR) circuit including a plurality of input selectors and a plurality of registers which are alternatively coupled in series with one another, wherein each of the plurality of input selectors combines an output signal of a previous stage register among the plurality of registers and an external input signal depending on the first and second input control signals and the feedback signal and provides an input signal for a next stage register among the plurality of registers.

Semiconductor device including multiple-input shift register circuit

A semiconductor device includes: first to Ninput terminals (where N is an integer equal to or greater than 2); and a redundant input terminal. When a Kinput terminal (where K is an integer ranging from 1 to N&#x2212;1) is defective among the first to Ninput terminals, (K+1)to Ninput terminals receive signals of Kto (N&#x2212;1)input terminals, respectively, and the redundant input terminal receives a signal of the Ninput terminal.

Semiconductor device

A semiconductor device includes a column command generation unit suitable for generating a column command delayed by a first delay time from a source command, in response to a first control signal and the source command, a bank address generation unit suitable for generating a bank address delayed by the first delay time from a bank source address, in response to the first control signal and the bank source address, a precharge command generation unit suitable for generating a precharge command delayed by a second delay time from the column command, in response to a second control signal and the column command, and a precharge bank address generation unit suitable for generating a precharge bank address delayed by the second delay time from the bank address, in response to the second control signal and the bank address.

Semiconductor device and semiconductor system having the same

A semiconductor memory device includes: a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.

Semiconductor memory device including stacked memory chips

A semiconductor memory device includes a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation clock in response to a first active pulse in a self-refresh operation exit mode, a second pre-charge control block suitable for generating a second control signal in response to an active command for an active operation in a self-refresh operation mode, and an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and disabling the second pre-charge control block in a self-refresh operation exit mode, wherein a pre-charge operation starts in response to the first and second control signals after the active operation. The semiconductor memory device may then be secured in a minimal time for stably performing an active operation during a self-refresh operation.

Semiconductor memory device and method for operating the same

A semiconductor memory device includes a plurality of banks, a plurality of compression blocks configured to compress a plurality of first read data respectively provided by the banks and output a plurality of second read data, a plurality of pipe latches configured to latch the second read data and output third read data in series, an output controller configured to receive the third read data from the pipe latches and sequentially output fourth read data in response to a plurality of bank addresses and a read enable signal, and a pad configured to transfer the fourth read data sequentially outputted from the output controller to an outside of the semiconductor memory device.

Semiconductor memory device

A semiconductor device may include first to fourth output lines, an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively, a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth input signals and represents whether the corresponding input signal is valid or not, and a signal transfer unit suitable for transferring the latched input signals, which are obtained by latching the input signals in response to the first to fourth clocks, to the first to fourth output lines based on a correspondence relationship that is decided based on a valid signal latch result of the valid signal latch unit.

Semiconductor device, semiconductor system including the same, and method for operating the same

A semiconductor memory device includes a pad configured to receive a first write data from outside of the semiconductor memory device, and a write circuit configured to generate a plurality of second write data which are to be written in memory cells of all banks to be tested in response to a test mode signal, data strobe signals, a write enable signal, and the first write data transferred through the pad.

A semiconductor device includes a delay line configured to delay a source clock by a delay equal to a first number of delay units in response to a delay control code and to generate a delayed source clock; a delay amount sensing unit configured to sense whether the delay amount of the delay line reaches a delay amount limit; a clock cycle measuring unit configured to measure the cycle of the source clock by counting a sampling clock in response to an output signal of the delay amount sensing unit, wherein a cycle of the sampling clock is equal to a second number of delay units; and a delay amount controlling unit configured to change the delay amount of the delay line in response to the measured cycle of the source clock as determined from an output signal of the clock cycle measuring unit.

Delay locked loop circuit and semiconductor device having the same

A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device.

A semiconductor integrated circuit includes a first semiconductor chip including a first output circuit which is enabled in a first operation mode and outputs a first output signal and a second output circuit which is enabled in a second operation mode and outputs a second output signal; a second semiconductor chip including a first input circuit which is enabled in the first operation mode and receives the first output signal and a second input circuit which is enabled in the second operation mode and receives the second output signal; and a common through chip via arranged to vertically penetrate through the semiconductor chip, be coupled with the first and second output circuits in one end and coupled with the first and second input circuits in the other end, and interface transfer of the first and second output signals which are enabled in different operation modes, including the first and second operation modes.

Semiconductor integrated circuit having stacked semiconductor chips and vias therebetween

A semiconductor device includes a first phase detector for detecting a phase of a second clock by comparing the phase of the second clock with the phase of the first clock, a second phase detector for detecting a phase of a clock obtained by delaying the second clock by a set delay amount, a third phase detector for detecting the phase of the second clock by delaying the first clock by the set delay amount, and a phase difference detection signal generator for setting a logic level of a phase difference detection signal corresponding to a phase difference between the first and second clocks detecting that the phase of the first or second clock is changed, and change the logic level of the phase difference detection signal.

Semiconductor device and delay locked loop circuit thereof

A data input device of a semiconductor memory apparatus includes: a differential amplifier configured to compare an input to a reference voltage and output a differential signal based on the comparison; and a control circuit configured to adjust a current driving capacity of the differential amplifier by turning on a first current path connected to the differential amplifier in response to a first enable signal and turning off a second current path connected to the differential amplifier in response to a second enable signal in a standby mode, wherein, during a time that a plurality of external command signals toggle back and forth between a status of all being high signals and a status of all being low signals repeatedly, the second enable signal is controlled to be maintained at a low state signal.

Data input device of semiconductor memory appartus and control method thereof

Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.

Semiconductor device capable of suppressing a coupling effect of a test-disable transmission line

A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required, or a smaller delay amount than a minimum delay amount of delay line is required. A control unit resets the delay locked loop according to the state of the delay line.

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Gyeonggi-do, South Korea

Young-Jun Ku