Samsung Electronics Co., Ltd.

Skhynix Inc.

Hynix Semiconductor Inc.

Md Healthcare Inc.

Yonsei University

Dongwoo Fine-chem Co., Ltd.

Sogang University Corporation

Korea Smart Card Co., Ltd.

Ewha University-Industry Collaboration Foundation

Young-Ju Kim

Dong-Uk Lee

Seungjun Bae

Keun-Soo Song

Hye Jung Kwon

Yoon-Joo Eom

Yoon-Keun Kim

Sang-hyup Lee

Jun-Young Choi

Dong-Seok Kang

Young Koo Jee

Mina Rho

Anil Agiwal

Young-Ho Kim

Young-Sik Kim

Sang-Hyun Han

Kyung-Hoon Lee

Jung-hyun Lee

Hae-Rang Choi

Seung-hoon Lee

Chae-Man Lim

Myeon-Kyun Cho

Michael Choi

Byungchul Kim

Sung-Chul Park

Sang-Min Ro

Soo-Young Kim

Hyuk-Joon Kwon

Sang-Jun Choi

Jong-Hyuk Kim

In-Hyuk Choi

Bok-Yeon Won

Kwan-Weon Kim

Su-a Kim

Dae-Sik Hong

Won-Hyoung Park

Yeon-Woo Kim

Yong-Hun Kim

Jin-Hyuk Lee

Sang-hoon Shin

Dai-Kwan Kim

Yongjae Lee

Su-Yeon Doo

Ranjeet Kumar Patro

Chang-Sik Kim

Hyung-jin Bae

Sang-Keun Han

Aravind V Iyer

Hyun-chul Yoon

Don-seon Lee

Suck-Ho Seo

Bong-gi Lee

Eun-seok Shin

Il-Sung Hong

Dong-Hyoun Son

Ji-Ryang Chung

Myoung-jin Oh

Ji-Suk Kwon

Kyeong-Jun Kim

Ranjitsinh Udaysinh Wable

Hye-Jung Kwon

Jong-Goo Kim

Won-Geun Shim

Ji-Young Hwang

Seung-Gil Jeon

Gyu-Seok Shim

Suyeon Doo

Woong-dai Kang

Abhijit Chandrashekhar Pathak

Ashok Subash

Amit Prabhudesai

Bum-Jae Lee

Ravindra Balkrishna Shet

Won-Hee Lee

Raghavendra Vaddarahalli Ramegowda

Nam-Kun Kim

Hyeong-Geun Kim

Ki-Soo Cho

Minhye Kim

Mahesh Anjanappa

Prasad Tirumala Sree Hari Vara Vadlapudi

Hyeonil Choi

Sungmin Kiem

Min-Woo Won

Ji-Hak Yu

Seok-Jae Lee

Byeong-Ho Shim

Jin-Woo Hwang

Kyu-Hong Cheong

Kangli Hao

Madhavan Vasudevan

Mahesh Malagouda Patil

M S S K Sharma

Shekhar Anantha Ambekar

Ho-jin Park

Kyoung-jun Moon

Subba Reddy Venkata Kota

Se-won Lee

Varunjith Therath Kainoth

Beom-soo Park

The present disclosure relates to an antenna element including: a dielectric layer; a radiation electrode arranged on an upper surface of the dielectric layer and including a first mesh structure; and a dummy electrode arranged on the upper surface of the dielectric layer and including a second mesh structure, in which at least one of the radiation electrode and the dummy electrode satisfies Equation 1, and an image display device including the same.

Antenna element and image display device including the same

A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

Memory device and operation method thereof

Memory device and method with data input

An electronic apparatus, according to various embodiments of the present invention, comprises: a first antenna of a first bandwidth; a second antenna of a second bandwidth which partially overlaps with the first bandwidth; a third antenna of the first bandwidth; a fourth antenna of the second bandwidth; a transmission/reception path corresponding to each of a plurality of bandwidths; a reception path corresponding to each of the plurality of bandwidths; and a path formation unit which forms a path such that any one of the first antenna and the third antenna is connected to the transmission/reception path, the other of the first antenna and the third antenna is connected to the reception path, and any one of the second antenna and the fourth antenna is connected to the transmission/reception path, and the other of the second antenna and the fourth antenna is connected to the reception path.

Electronic apparatus and control method therefor

A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.

Memory system for adjusting clock frequency

An apparatus and method for providing one or more protocols for one or more electronic devices are provided. The method includes establishing, by an electronic device configured to provide a framework interface by executing instructions stored in a memory, one or more physical channels with an external electronic device, using one or more communication modules, executing, by the electronic device, two or more application programs to interface with the framework interface, and communicating, via the framework interface, data from the two or more application programs through the one or more physical channels to the external electronic device, using at least one logical channel or session for a respective one of the two or more application programs.

Electronic device using logical channels for communication

A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.

A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.

Memory device including detection clock pattern generator for generating detection clock output signal including random data pattern

Provided is a composition for the treatment of pregnancy-associated diseases, and more particularly, to a pharmaceutical composition for the prevention or treatment of premature delivery or breast cancer. The pharmaceutical composition including extracellular vesicles derived from bacteria belonging to the genusas an active ingredient may induce pregnancy or prevent premature delivery of pregnant women, may be used to prevent or treat pregnancy-associated diseases such as breast cancer, and may be used to diagnose a risk of premature delivery by measuring the amount of extracellular vesicles derived from bacteria belonging to the genusin pregnant women.

Method for diagnosing premature delivery in a pregnant woman

A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

Semiconductor integrated circuit including master chip and slave chip that are stacked

The present invention relates to a method for predicting causative factors (bacteria) of serious bacterial infectious diseases in a clinical sample containing bacteria-derived nano-sized extracellular vesicles, that is, nanovesicles, through the analysis of the genes contained in the nanovesicles. According to the present invention, information on bacteria of serious bacterial infection can be provided, a causative factor of the bacterial infection can be predicted, and the resistance of the bacteria to antibiotics can be predicted.

Method for identifying pathogens of bacterial infectious diseases by using bacteria-derived nanovesicles

A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

Memory device and method of disposing conduction lines of the same

Semiconductor integrated circuit

The present invention relates to an electronic payment means activating method and an activating server thereof. In the electronic payment means activating method, a usage approval of the inactive electronic payment means is requested by using first identification information of the inactive electronic payment means and personal user information of the user terminal, the first identification information is authenticated to determine usage approval of the active electronic payment means, a class of a user is detected by using the personal user information, a first parameter value corresponding to the detected class of the user and a usage approval message are provided to the user terminal, the first parameter value is established in the user terminal, the electronic payment means is activated, and a fare according to the first parameter value is paid by the electronic payment means.

Method to activate electronic payment unit in mobile terminal and activity server thereof

Semiconductor integrated circuit including at least one master chip and at least one slave chip

Growing community of inventors

Suwon-si, South Korea

Young-Ju Kim