Texas Instruments Corporation

Young-Joon Park

Jeffrey Alan West

Qi-Zhong Hong

Abbas Ali

Srikanth Krishnan

Palkesh Jain

Dhishan Kande

Ki-Don Lee

Kyle McPherson

Siva Prakash Gurrum

Jungwoo Joh

Richard Allen Faust

Ennis Takashi Ogawa

Andrew Tae Kim

Guru Chakrapani Prasad

A semiconductor device a strapped interconnect line, which in turn includes a first interconnect line at a first level above a semiconductor substrate, and a second interconnect line at a second level above the interconnect substrate. A dielectric capping layer is located directly on the first interconnect line. A plurality of strapping vias are connected between the first interconnect line and the second interconnect line. Each of the strapping vias extends from a first side of the first interconnect line to a second side of the second interconnect line.

Strapped copper interconnect for improved electromigration reliability

A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.

Metal interconnect processing for an integrated circuit metal stack

A method of fabricating an integrated circuit (IC) includes forming a metal interconnect stack on substrate that includes a plurality of product die each having a plurality of transistors connected together to implement a circuit function. The forming the metal interconnect stack includes depositing a metal interconnect layer comprising aluminum on a barrier layer at a first temperature. After depositing the metal interconnect layer, the metal interconnect stack is annealed in a non-oxidizing ambient at a maximum annealing temperature that is&#x3c;the first temperature. After the annealing, a pattern is formed on the metal interconnect layer, and at least the metal interconnect layer is etched.

Metal interconnect processing for a non-reactive metal stack

A method of computing a peak current density specification (j) for an electrical conductor line of an integrated circuit (IC) resulting from conducting pulsed electrical current represented as a current waveform. An on-time (t) is identified for the current waveform based on a current density being greater than or equal to (&#x2267;) a predetermined current density level. The jis computed for the electrical conductor line using a jmodeling equation which includes the tfor the current waveform and a thermal time constant (&#x3c4;) for the electrical conductor line.

On-time based peak current density rule and design method

A resistor is formed on field oxide with a portion of the resistor body configured to overlap an active region in an integrated circuit (IC) substrate to provide heatsinking for the resistor body. In one embodiment, cooling fingers extend from the resistor body beyond the field oxide to overlap the active region. In another embodiment, minor areas of the resistor body overlap the active region. The resistor body may be formed of polycrystalline silicon (polysilicon), silicided polysilicon, or metal. An oxide having greater thermal conductance than the field oxide is formed between the overlapping parts of the resistor body and the active region.

IC resistor formed with integral heatsinking structure

An integrated circuit is described. The integrated circuit, comprising: a central processor; a memory; and an electromigration compensation system associated with a plurality of leads within the integrated circuit, wherein the electromigration compensation system causes the plurality of leads to have interlocking, horizontally tapered ends that substantially reduces electromigration divergence and consequently lead resistance and circuit shorting.

Electromigration compensation system

A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit, including: calculating a net effective current density of the via node. Calculating the net effective current density including determining a sum of effective current densities for individual leads that are coupled to the via node. Leads configured to transfer electrons away from said via node are assigned a positive polarity of the effective current density. Leads configured to transfer electrons towards the via node are assigned a negative polarity of the effective current density.

Via-node-based electromigration rule-check methodology

A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve, an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to protruding TSV tips is on a portion of the sidewalls of protruding TSV tips. The passivation layers is absent from a distal portion of protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends which cover a portion of the TSV sidewalls, are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is &#x2267;25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

IC devices having TSVS including protruding tips having IMC blocking tip ends

Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal paths based on computed parameter values for the corresponding metal path. A reliability analysis for the circuit is performed based on the apportioning. In an embodiment, metal paths which predominantly carry currents with an average value less than a threshold are excluded from being considered as contributors to EM degradation.

Budgeting electromigration-related reliability among metal paths in the design of a circuit

A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve and an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to the protruding TSV tips is on a portion of the sidewalls of the protruding TSV tips. The passivation layers is absent from a distal portion of the protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends including a first metal layer including a first metal other than solder and a second metal layer including a second metal other than solder that covers the exposed tip portion. The bulbous distal tip ends cover a portion of the TSV sidewalls and are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is &#x2267;25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

A semiconductor deviceincludes a metal lineformed in a first dielectric layer. A capping layeris formed the metal line. A second dielectric layeris formed over the first dielectric layerand the metal line. A first viais formed in the second dielectric layerand in contact with the metal line. A second viais formed in the second dielectric layerand in contact with the metal line, and is positioned a distance away from the first via. An electrically isolated viais formed in the second dielectric layerand in contact with the metal lineand in between the first viaand the second via. A third dielectric layeris formed over the second dielectric layer. First and second trenchesare formed in the third dielectric layerand in contact with the first viaand the second via, respectively. An isolated trenchis formed in the third dielectric layer and in contact with the isolated via. The isolated viamitigates void formation and/or void migration during operation/conduction with electrons traveling from the first trenchto the second trenchvia the metal line

Electrically inactive via for electromigration reliability improvement

The present invention provides, in one embodiment, An integrated circuit device (). The integrated circuit device () comprises a circuit feature () located over a semiconductor substrate () and an insulating layer () located over the circuit feature (). A protective overcoat () is located over the insulating layer () and a metal structure () is located over the protective overcoat (). The metal structure () is electrically connected to the circuit feature () by an interconnect (). The metal structure () is coated with a conductive encasement (), the conductive encasement () terminating at a perimeter () of the metal structure (). Another embodiment of the invention in a method of manufacturing an integrated circuit device ().

Selectively encased surface metal structures in a semiconductor device

An embodiment of the invention is a method of manufacturing copper interconnectson a semiconductor waferwhere an electroplating process is used to deposit a first layer of copper grainshaving an initial grain size and a second layer of copper grainshaving a different initial grain size.

Two step semiconductor manufacturing process for copper interconnects

Isolated metal structures ( ), ( ) are formed adjacent to terminated metal lines ( ), ( ) that are connect by a via ( ). The isolated structures ( ), ( ) act to suppress the stress created in the terminated metal lines ( ), ( ) during thermal cycling.

Growing community of inventors

Plano, TX, United States of America

Young-Joon Park