Samsung Electronics Co., Ltd.

Young-Joo Jeon

Daewon Ha

Kwang-woo Lee

Memory devices include a row decoder, a first variable resistance memory cell connected to a first bit line and connected to the row decoder by a word line and a second variable resistance memory cell connected to a second bit line and connected to the row decoder by the word line. The memory devices further include a bit line select circuit coupled to the first and second bit lines and configured to compensate for a difference in word line resistance between the row decoder and the respective first and second memory cells. In some embodiments, the bit line select circuit includes first and second transistors configured to selective respective ones of the first and second bit lines and the first and second transistors have different resistances that compensate for the difference in word line resistance.

Variable resistance memory devices compensating for word line resistance

A memory cell device is provided which includes a substrate, a plurality of unit memory cells connected between a word line and respective bit lines, where each memory cell including a resistance variable element, such a phase-change element, and a diode connected in series between the word line and the respective bit line, and a biasing circuit which applies a biasing voltage to the substrate to decrease a current flow in the word line.

Growing community of inventors

Suwon-si, South Korea

Young-Joo Jeon