Korea Electronics Technology Institute

Young Jong Jang

Byung Soo Kim

Young Kyu Kim

The present disclosure relates to a method for classifying instructions according to the number of operands required for processing-in-memory instruction processing, and a computing device applying same. Efficient instruction processing in a processing-in-memory may include identifying the number of operands required when processing an instruction queuing to be processed, interpreting the instruction queuing to be processed and processing an instruction corresponding to the identified number of required operands. When the number of required operands is 0, the instruction interpretation may interpret the instruction queuing to be processed as a WRITE instruction, and the instruction processing may execute memory writing. When the number of required operands is not 0, the instruction processing may execute memory reading in an internal memory of the processing-in-memory by the same number of times as the number of operands required in the instruction interpreted in the instruction interpretation.

Processing-in-memory control method for efficient instruction processing and computing device applying same

This application relates to a method and apparatus for processing a new read-write-operation instruction added to an instruction set to maximize the performance of processing-in-memory (PIM). The read-write-operation instruction performs reading and writing on an operation result of the PIM by returning the operation result of the PIM to a computer system and, at the same time, writing the operation result to a destination address. An instruction processor in PIM includes a response data selector and a finite state machine to process the read-write-operation instruction. The response data selector includes a selector configured to select one of a response data signal and an operation result, and a three-phase buffer configured to allow or disallow response data. The finite state machine of the instruction processor outputs a response permission signal and a response selection signal for controlling the buffer and the selector.

Method and apparatus for processing read-write-operation instruction in processing-in-memory

This application relates to a memory management method for maximizing processing-in-memory (PIM) performance and reducing unnecessary DRAM access time. In one aspect, when processing a PIM instruction packet, an instruction processing unit secondarily processes a request for access to a destination address at which read and write actions of an internal memory are likely to be sequentially performed. By secondarily requesting the destination address, a row address of an open page of the internal memory may match a row address to which a PIM instruction packet processing result is written back. Also, the instruction processing unit inside the PIM maintains memory write and read addresses that have previously requested. The instruction processing unit compares the address of a packet to be processed to the maintained previous memory address and informs a memory controller about the comparison result through a page closing signal.

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Yongin-si, South Korea

Young Jong Jang