Hynix Semiconductor Inc.

Young-Jin Yoon

Kwan-Weon Kim

Seong-Hoon Lee

Si-Hong Kim

A semiconductor device for performing an N-bit prefetch operation, N being a positive integer includes a data strobe buffering means for generating N number of align control signals based on a data strobe signal and a external clock signal; a receiving block in response to N&#x2212;1 number of the align control signals for receiving N-bit data and outputting the N-bit data in a parallel fashion; and a outputting block in response to the remaining align control signal for receiving the N-bit data in the parallel fashion and synchronizing the N-bit data with the remaining align control signal having a N/2 external clock period to thereby generating the synchronized N-bit data as a prefetched data.

Synchronous memory device having advanced data align circuit

A synchronous memory device which generates a data output enable signal corresponding to a set CAS latency mode including: a control clock generator for generating an A-type first control clock and a B-type first control clock; a first redundancy enable signal generator for shifting an internal read signal by a predetermined interval in synchronization with one of the A-type first control clock and the B-type first control clock and generating a plurality of first redundancy enable signals; a second redundancy enable signal generator for synchronizing the plurality of first redundancy enable signals with a DLL clock and generating a plurality of second redundancy enable signals; and an output enable signal generator for selecting one redundancy enable signal corresponding to the set CAS latency mode among the first redundancy enable signals and the second redundancy enable signals and generating the selected redundancy enable signal as the data output enable signal.

Memory device with improved output operation margin

A semiconductor memory device minimizes a data accessing time. For the purpose, it includes a first control signal generator for producing a first control signal by logically combining a pipelatch-in signal and a start-odd start-even data output control signal, a second control signal generator for producing an odd control signal by logically combining an odd data enable signal for outputting odd-numbered data and a control signal for accessing the odd-numbered data in response to a start address, and generating an even control signal by logically combining an even data enable signal for outputting even-numbered data and a control signal for accessing the even-numbered data in response to the start address, a first accessing unit for accessing input data in response to the first control signal, a latch for temporarily storing data outputted from the first data accessing unit, and a second accessing unit for secondly accessing the data stored at the latch, thereby outputting secondly accessed data.

Semiconductor memory device for reducing data accessing time

A semiconductor memory device includes an advanced prefetching block for prefetching more bit data at once and effectively arranging the prefetched data so as to reduce an address access time of the semiconductor memory device. The semiconductor memory device having four pipelining latches for prefetching 4-bit data outputted from at least one bank in response to a start address of the 4-bit data and control signals includes a first data multiplexing unit, a second data multiplexing unit, a third order multiplexing unit and a forth order multiplexing unit.

Semiconductor memory device having advanced prefetch block

A synchronous memory device which comprises global I/O lines for data input and output from and to a memory core and a pipeline latch circuit for latching data from the global I/O lines. The synchronous memory device includes a circuit that precharges the global I/O lines when a read command signal interrupts a write operation signal, and disables the pipeline latch circuit in order to prevent write data on the global I/O lines from being latched in the pipeline latch circuit. Accordingly, the write data is prevented from being transferred to the pipeline latch circuit at an early stage of the read operation.

Growing community of inventors

Ichon-shi, South Korea

Young-Jin Yoon