Silicon Works Co., Ltd.

Skhynix Inc.

Young Jin Woo

Young Sik Kim

Ji Hun Kim

Hoo Hyun Cho

Kong Soon Park

Seung Jong Lee

Jin Hee Jeon

Tae Hyun Kim

Nam Kyeong Kim

Young Suk Son

Dae Keun Han

Wanyuan Qu

Won Yeol Choi

Hyun Jin Jeon

Byeong Jae Park

Won Suk Jang

Tae Kyu Nam

Hong Kyu Choi

Jin Soo Byeon

Kyoung Chul Yang

A memory device includes a page with plurality of memory cells and a peripheral circuit that performs at least one program loop. The at least one program loop includes a program voltage applying phase for applying, during a program operation, a program voltage to a word line to which the plurality of memory cells are coupled and a program verify phase for determining whether a selected memory cell among the plurality of memory cells has been completely programmed. The memory device includes control logic that controls the peripheral circuit to: perform an auxiliary verify operation of applying an auxiliary verify voltage to the word line; perform a main verify operation of applying a main verify voltage larger than the auxiliary verify voltage to the word line; and determine a fail of the program operation, based on verify data obtained by performing the auxiliary verify operation and the main verify operation.

Memory device and operating method thereof

An embodiment provides a power management integrated circuit including, inside thereof, a capacitor configured to simulate an inductor and multiple current sources configured to simulate an inductor voltage, wherein the power management integrated circuit is capable of testing whether an internal element normally operates without a separate test device including an inductor.

Power management integrated circuit

An embodiment provides a technology of sharing electric charges of two or more flying capacitors in a time interval in which a plurality of flying capacitors are floated, so as to control the charging/discharging balance of the flying capacitors, in a step-up converter.

Multi-level step-up converters with flying capacitor

The present invention attenuates noise appearing at neighboring electrodes by causing a rising edge of one clock signal to be synchronized with a falling edge of another one clock signal when a clock signal for gate driving is generated.

Gate driving circuit, level shifter, and display device

A pass switch circuit for transferring the voltage of an input node to an output node and a method of controlling the pass switch circuit are disclosed herein. The pass switch circuit includes a pass switch, a first capacitor, and a first switch. The pass switch transfers a voltage level from an input node to an output node. The first capacitor is configured such that the node of one side thereof has a first level of voltage when the voltage of the control node of the pass switch is in a first state. The first switch connects the node of the one side of the first capacitor with the control node of the pass switch.

Pass switch circuit with improved time response characteristics and method of controlling same

A switching power supply may include: an inductor connected to an input voltage terminal; a first switch configured to form a first electrical path between the inductor and an output voltage terminal; a second switch configured to form a second electrical path between the inductor and a ground voltage terminal; a negative current sensor configured to sense an inductor current flowing through the first electrical path, and generate an over-current protection signal when the inductor current is sensed as a negative current equal to or more than a preset value; and a controller configured to enable a discontinuous conduction mode (DCM) when the over-current protection signal is generated, and turn off the first switch and turn on the second switch, in response to the enabled DCM.

Switching power supply

A level shifter circuit with improved time response and a control method thereof are disclosed herein. The level shifter circuit includes the output stage circuit of a level shifter and a booster circuit. The output stage circuit of the level shifter includes a first pass switch configured to transfer a voltage level of the first power supply of the level shifter to an output node, and a second pass switch connected between a second power supply and the first pass switch. The booster circuit accelerates the switching operation of the level shifter by accelerating a time response during the turning on or off operation of the first pass switch using charge sharing between a first capacitor and the parasitic capacitance of the control node of the first pass switch, which occurs via a first switch.

Level shifter circuit with improved time response and control method thereof

Disclosed herein are a switching mode converter and a method for controlling thereof. The switching mode converter includes a switching element, a bootstrap capacitor, and a control unit. The switching element is connected between one side of a first semiconductor device, another side of the first semiconductor device is connected to a ground, and an input power. The bootstrap capacitor is configured such that one side of the bootstrap capacitor is connected to the one side of the first semiconductor device. The control unit controls the output current or output voltage of a common charge pump provided to the switching element and the bootstrap capacitor in order to control the charging state of the bootstrap capacitor and the gate voltage of the switching element.

Switching mode converter having 100% duty cycle mode and method for controlling thereof

The present invention provides a gamma voltage supply circuit capable of stably supplying a gamma voltage in response to the change of external voltage and a power management IC including the same. The gamma voltage supply circuit generates a regulating voltage using an internal voltage which is not influenced by the variation in load of a source driver IC, and generates a gamma voltage using the regulating voltage.

Gamma voltage supply circuit and method and power management IC

The present invention relates to a switch circuit, and more particularly, to a switch circuit that uses an LDMOS (lateral diffusion metal oxide semiconductor) device inside an IC (Integrated Circuit). In the switch circuit that uses the LDMOS device according to an embodiment of the present invention, a gate-source voltage (V) of the LDMOS device may be stably controlled through a current source and resistances, the characteristics of a switch may be maintained regardless of the voltages of both terminals (A and B) by using an N-type LDMOS and a P-type LDMOS in a complementary manner, and the current generated by the current source is offset inside the switch without flowing to the outside of the switch.

Switch circuit using LDMOS device

Switch circuit using LDMOS element

A nonvolatile memory device includes memory cell blocks each configured to comprise memory cells erased by an erase voltage, supplied to a word line, and a bulk voltage supplied to a bulk, a bias voltage generator configured to generate a first erase voltage, having a first pulse width and a first amplitude, in order to perform the erase operation of the memory cells and a second erase voltage, having a second pulse width narrower than the first pulse width and a second amplitude lower than the first amplitude, in order to perform an additional erase operation if an unerased memory cell is detected after the erase operation is performed, and a bulk voltage generator configured to generate the bulk voltage.

Growing community of inventors

Daejeon, South Korea

Young Jin Woo