Samsung Electronics Co., Ltd.

Young Jin Noh

Yong Woo Lee

Bio Kim

Seung Bo Shim

Jun Kyu Yang

Ji Soo Im

Jae Ho Choi

Jae Young Ahn

Doug Yong Sung

Woo Jin Jang

Cheon Lee

Peter Byung H Han

Masato Horiguchi

Kyong Won An

Dong Chul Yoo

Hyeong Mo Kang

Jae Hoon Kim

Seung Hyun Lim

Jeon Il Lee

Eun Yeoung Choi

Won Young Choi

Sung Moon Park

Hyung Kyu Choi

Kyung Sun Kim

Kwang Min Park

Jae Hyun Yang

Jun Soo Lee

Seung Kyu Lim

Kyeong Seok Jeong

Yoshihisa Hirano

Plasma processing equipment includes a chuck stage for supporting a wafer and including a lower electrode, an upper electrode disposed on the chuck stage, an AC power supply which applies first to third signals having different magnitudes of frequencies to the upper electrode or the lower electrode, a dielectric ring which surrounds the chuck stage, an edge electrode located within the dielectric ring, and a resonance circuit connected to the edge electrode. The resonance circuit includes a filter circuit which allows only the third signal among the first to third signals to pass, and a series resonance circuit connected in series with the filter circuit and having a first coil and a first variable capacitor connected in series and grounded.

Plasma processing equipment

A plasma processing apparatus may include a lower electrode supporting a wafer; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring. The focus ring may include a lower region and an upper region disposed on the lower region, and the upper region increases in electrical conductivity as the upper region is closer to the lower region.

Plasma processing apparatus

An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

Integrated circuit memory devices having impurity-doped dielectric regions therein and methods of forming same

A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.

Semiconductor device

A plasma processing apparatus including an electrostatic chuck supporting a wafer; a focus ring disposed to surround an outer circumferential surface of the wafer; an insulation ring disposed to surround an outer circumferential surface of the focus ring; and an edge ring supporting lower portions of the focus ring and the insulation ring, the edge ring being spaced apart from the electrostatic chuck and surrounding an outer circumferential surface of the electrostatic chuck; wherein the edge ring includes a flow channel containing a fluid therein.

A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.

Semiconductor device with a tunneling layer having a varying nitrogen concentration, and method of manufacturing the same

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Suwon-si, South Korea

Young Jin Noh