Samsung Electronics Co., Ltd.

Young-jin Chung

Jin-Aeon Lee

Jin-su Hyun

Jae-Chul Park

Hong-mook Choi

Jong-hoon Shin

Yun-Ho Youm

Hye-soo Lee

Yoon-bum Seo

Byeong-Whee Yun

Yong-Ha Park

Kil-Whan Lee

Ki-Seok Bae

Min-Su Lim

In-goo Heo

Yun-Kyoung Kim

Mahn-Gee Park

An SOC includes a security processor. The security processor includes an encryption/ECC encoding processor configured to perform an encryption operation on data using Metadata and to generate ECC data by performing ECC encoding processing on encrypted data and the Metadata, a decryption/ECC decoding processor configured to extract the encrypted data and the Metadata by performing ECC decoding processing using the ECC data and to recover the data by performing a decryption operation on the encrypted data using the Metadata, and an address controller configured to receive a first address related to storage of the data, to generate a second address based on the first address, and to perform an address generating operation identifying a same region in memory for storing the Metadata and the ECC data based on the second address.

System on chip and memory system including security processor with improved memory use efficiency and method of operating system on chip

A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.

Security devices, electronic devices and methods of operating electronic devices

Digital logic processing devices capable of reduced power consumption may be provided. A digital logic processing device may include one or more processing elements, an input FIFO for storing data, a processing unit, and a clock controller circuit. The processing unit may process data from the input FIFO and the clock controller circuit may control a clock signal supplied to the input FIFO and the processing unit. The clock controller circuit may monitor whether there is data to be transferred to the input FIFO and states of the input FIFO and the processing unit and may control the clock signal.

Instantaneous data-driven clock-gating device and hard-wired streaming processing system including the same

A memory controller having graphic processing function that includes a graphic processing unit operating in response to a selection signal from a master, and a memory interface for storing outputs of the graphic processing unit in an external memory at and receiving graphic data from the external memory to provide the graphic data to the graphic processing unit.

Memory controller with graphic processing function

An apparatus according to an example embodiment of the present invention, may process data of a present span. During processing, data corresponding to an address of the start data of the next span may be prefetched from the external memory device based on information related to the presently processed data. The prefetched data may store in the cache memory.

Apparatuses and methods for processing graphics and computer readable mediums storing the methods

Provided are a memory controller for controlling a refresh cycle of a memory and a method thereof. In this method, a temperature measure command is generated to measure an operating temperature of the memory. Next, a measured temperature in response to the temperature measure command is received. Then, a temperature difference between the measured temperature and a reference temperature is detected if the measured temperature is different from the reference temperature to change the refresh cycle according to the temperature difference, and if the measured temperature is equal to the reference temperature the method returns to the temperature measure command generating step. Thereafter, a refresh command is applied to the memory in response to the changed refresh cycle.

Memory controller for controlling a refresh cycle of a memory and a method thereof

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Seongnam-si, South Korea

Young-jin Chung