Samsung Electronics Co., Ltd.

Young-jin Choi

Satoru Yamada

Seung-Uk Han

Yong-il Kim

Kyo-Suk Chae

Jin-sub Lee

Nam-Ho Jeon

Woo-song Ahn

Han-kyu Seong

Won Sik Kim

Kyu-Hyun Lee

Sung-ro Go

Wook-Je Kim

Jay-Bok Choi

Jong-won Kim

Sang-Yeon Han

Min-Chul Park

Gwang-ho Lee

Moon-noh Lee

Il-Hong Suh

Mi-Jeong Jang

Ju-Young Huh

Hong-rok Kim

Wan-kyun Chung

Jun-young Ko

Po-seong Park

A light-emitting diode (LED) package includes: a reflective structure including a cavity, a bottom portion having a through hole, and a sidewall portion surrounding the cavity and the bottom portion and having an inclined inner side surface; an electrode pad inserted into the through hole; an LED on the bottom portion in the cavity, the LED including a light-emitting structure electrically connected to the electrode pad and a phosphor formed on the light-emitting structure; and a lens structure filling the cavity and formed on the reflective structure.

Light-emitting diode package and method of manufacturing the same

A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

Gate electrode and gate contact plug layouts for integrated circuit field effect transistors

Semiconductor devices are provided including a gate across an active region of a substrate; a source region and a drain region in the active region on either side of the gate and spaced apart from each other; a main channel impurity region in the active region between the source and drain regions and having a first channel impurity concentration; and a lightly doped channel impurity region in the active region adjacent to the drain region. The lightly doped channel impurity region has the same conductivity type as the main channel impurity region and a second channel impurity concentration, lower than the first channel impurity concentration. The lightly doped channel impurity region and the main channel impurity region contain a first element. The lightly doped channel impurity region also contains a second element, which is a different Group element from the first element.

Semiconductor devices having lightly doped channel impurity regions

A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

Semiconductor device having line-type trench to define active region and method of forming the same

An anti-fuse device includes a gate electrode on a semiconductor substrate, a gate insulating layer between the semiconductor substrate and the gate electrode, junction regions in the semiconductor substrate adjacent the gate electrode, and at least one anti-breakdown material layer between the junction regions, the gate insulating layer being between the gate electrode and the anti-breakdown material layer.

Anti-fuse device and semiconductor device and system including the same

A method of fabricating a semiconductor device is disclosed, the method generally including the steps of: forming a gate dielectric layer on a semiconductor substrate; forming a gate electrode on the gate dielectric layer; forming an etch stop layer on the gate electrode; forming a capacitor on the semiconductor substrate adjacent to the gate electrode; after forming the capacitor, forming a contact hole passing through the etch stop layer on the gate electrode; and, diffusing deuterium into the gate dielectric layer through the contact hole.

Method of fabricating semiconductor device using deuterium annealing

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate.

Semiconductor device including transistor and fuse circuit and semiconductor module including the same

An apparatus to remove periodic disturbances in a recording medium having large eccentricity and deflection mass includes an actuator to change a position of a pickup in response to a combination of first and second compensation signals, an error detector to detect an error between positions actuator and the recording medium, a first compensator to receive the detected error and to output the first compensation signal that the actuator uses to actuate the pickup along the recording medium in upper and lower directions, and right and left directions; and a second compensator to output the second compensation signal from which the disturbance has been removed, to combine the compensated error and previous first and second compensation signals, and to filter the combined result at a predetermined bandwidth.

Apparatus and method of removing disturbances during optical recording and/or reproducing

An apparatus for cutting tie bars of semiconductor packages unloads the semiconductor packages by continuously blowing air against the side of the packages after the tie bars are cut and the semiconductor packages are separated from lead frames. The packages are blown into a guide track which feeds into a storage tube. As a result, damage to the packages due to mechanical abrasion which may result from unloading with a pusher bar is prevented. Furthermore, the time required for unloading the semiconductor packages is reduced.

Apparatus for cutting tie bars of semiconductor packages

Growing community of inventors

Hwaseong-si, South Korea

Young-jin Choi