Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Lg Chem, Ltd

Samsung Electro-mechanics Co., Ltd.

Young-Jin Cho

Sang-moon Lee

Young-In Hwang

Ki-ha Hong

Deok-Young Choi

Sun-Young Lim

Eui-chul Hwang

Dong-Gyu Kim

Jae-Geun Park

Byung-Yul Choi

Yong-Jae Kim

Eun Chu Oh

Tae-wan Kim

In-Jun Hwang

Kee-won Kim

Wang-Jo Lee

Dong-Yang Lee

Oh-seong Kwon

Jang-Seok Choi

Jae-Hoon Lee

Young-Sik Kim

Yong-Sung Park

Jung-hyun Lee

Young-Soo Park

Sangyong Yoon

Won-Ho Lee

Chul-Kyu Kang

Dong-Kyu Kim

Jin-ha Kim

Yong-Ho Lee

Sung-Chul Lee

Tak-Young Lee

Dong-Hyun Kim

Kyoung-yeon Kim

Jin-Gon Oh

Hyun-Sik Kim

Yo-sep Min

Ki-Soo Lee

Hyunsik Kim

Sun-Ae Seo

Heon-Yong Kwon

Dong-woo Lee

Dae-Sik Hong

Kyoung-Jin Park

Hyun-Jong Shin

Jeong-ho Lee

Hak-sun Kim

Joon-Hee Cho

Young-Kwang Yoo

Yeon-Shick Yoo

Soon-Suk Hwang

Young-geun Lee

Bu-il Nam

Yeji Nam

Min-ho Kil

Keun-Bong Lee

Ung-Hwan Pi

Doo-Yeun Jung

Nari Lee

So-Hyun Lee

Dong-Gi Lee

Ju-yun Jung

Hee-Chang Cho

Sung-Sik Park

Ji-Hye Kong

Seong-hoon Woo

Gyo-Hyun Hwang

Moo-Youn Park

Hyun-Kuk Noh

Dong-Heui Jang

Sung-yong Seo

Young-Hyun Choe

Min-suk Kim

Jun-Won Kim

Kwang-Ho Park

Jeong-yeal Kim

Se-Yeon Jang

Kun-jeong Lee

Eui-hyeok Kwon

Jae-geun Park

Chul-seung Lee

Duk-Ki Kim

Hyun-jong Shin

Ju-yeon Park

Duk-ki Kim

Young-hyun Choe

Sung-chul Lim

Ji-Cheol Hong

Oh-Sung Byun

Kae-won Kim

Jong-Min Jung

Yun-Ji Hur

Hee-hyun Nam

Hong-Yeon Kim

Youn-Ho Hwang

Yeon-Shick Petrochemicals & Polymester R&D Yoo

Joo-Yeon Park

Young-Hyun Da-706 Lg Chemical Satatik Choe

Soo-Jeong Lee

An operation method of a nonvolatile memory device which includes a memory block having wordlines includes performing an erase on the memory block, performing a block verification on the memory block by using a 0-th erase verification voltage, performing a delta verification on the memory block by using a first erase verification voltage different from the 0-th erase verification voltage when a result of the block verification indicates a pass, and outputting information about an erase result of the memory block based on the result of the block verification or a result of the delta verification. The delta verification includes generating delta counting values respectively corresponding to wordline groups by using the first erase verification voltage, generating a delta value based on the delta counting values, and comparing the delta value and a first reference value.

Operation method of nonvolatile memory device

A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

Memory system with multiple channel interfaces and method of operating same

Provided is an organic light-emitting display apparatus and a method of repairing the same. The organic light-emitting display apparatus includes: an emission device comprising a plurality of sub-emission devices; an emission pixel circuit configured to supply a driving current to the emission device; a dummy pixel circuit configured to supply the driving current to the emission device; and a repair line coupling the emission device to the dummy pixel circuit, wherein the emission device is configured to receive the driving current from the emission pixel circuit or the dummy pixel circuit.

Organic light-emitting display apparatus and method of repairing the same

An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

Memory system and electronic device

A memory system for performing a recovery operation is provided. A memory system includes a memory device including a plurality of memory cells constituting a plurality of sub-sets, and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating a number of read operations performed by the memory device for each of the plurality of sub-sets, and to perform a recovery operation on a sub-set, among the plurality of sub-sets, based on the read count corresponding to the read count. Each of a plurality of sub-sets includes a plurality of pages. Each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells.

Memory controller performing recovery operation, operating method of the same, and memory system including the same

Provided are a memory controller determining degradation in endurance, a memory system including the memory controller, and a method of operating the memory controller. The memory controller includes: an error correction code (ECC) circuit configured to detect an error from data read from a memory device; and an endurance determination circuit configured to check a first counting value indicating a number of writing operations on the memory device and a second counting value indicating, based on the data read from the memory device, at least one of: a number of first memory cells of the memory device, each of the first memory cells having an error and a number of second memory cells of the memory device in a certain logic state, and configured to perform a first determination operation for determining whether endurance of the memory device has degraded based on a checking result.

Memory controller determining endurance degradation, memory system including the same, and method of operating the memory controller

A memory controller is provided. The memory controller includes an error correction code (ECC) circuit configured to correct an error of a read codeword provided from a memory device, the ECC circuit including: a codeword combination generator configured to receive a first read codeword including a plurality of first read codeword bit values that are read from a first region of the memory device, generate a change codeword by changing values of one or more of the plurality of first read codeword bit values, and provide a codeword combination including the change codeword; and an ECC decoder including a plurality of ECC engines, wherein the ECC decoder is configured to perform ECC decoding in parallel on a plurality of codewords included in the codeword combination.

Memory controller including error correction code circuit, memory system including the memory controller, and operating method of the memory system

A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.

Memory module, memory controller and systems responsive to memory chip read fail information and related methods of operation

A method of interfacing a memory controller and a memory device in a memory system includes transmitting a control signal between the memory controller and the memory device using a time division multiplexing (TDM) communication process, and transmitting data between the memory controller and the memory device using a serializer/deserializer (SERDES) communication process. Data communication in the memory system is performed via a physical channel and a plurality of virtual channels corresponding to the physical channel.

Memory system, memory interfacing device, and interfacing method performed in the memory system

An organic light-emitting display apparatus includes: a plurality of emitting pixels coupled to a plurality of scan lines extending in a row direction and a plurality of data lines extending in a column direction; a plurality of dummy pixels arranged in the row direction; a plurality of first repair lines extending in the column direction, that are coupled to the plurality of dummy pixels, and that are adapted to be coupled to the plurality of emitting pixels; a plurality of second repair lines extending in the column direction, and that are coupled to the plurality of dummy pixels; and a plurality of repair switching devices arranged in a matrix array and adapted to be coupled to the plurality of scan lines and the plurality of second repair lines and adapted to be coupled to the plurality of data lines.

Organic light-emitting display apparatus having sub-dummy pixels

A display apparatus includes at least one pixel in a display area, a driving circuit disposed in a peripheral area adjacent the display area, the peripheral area including a first fan-out area and a second fan-out area disposed between the first fan-out area and the display area, a first fan-out line disposed in the first fan-out area and the second fan-out area, and fanned out from the first fan-out area to the display area, a second fan-out line disposed in the second fan-out area, and fanned out from the second fan-out area to the display area, a first horizontal power line disposed in the second fan-out area, and a second horizontal power line disposed in the first fan-out area, and electrically connected to the second fan-out line.

Display apparatus

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Seoul, South Korea

Young-Jin Cho