Samsung Electronics Co., Ltd.

Young-Hoon Sohn

Yu-sin Yang

Sang-kil Lee

Kwang-il Park

Jin-Woo Lee

Chung-sam Jun

Si-Hong Kim

Yong-Gwon Jeong

Yong-Deok Jeong

A defect inspection apparatus comprises a table on which a substrate is placed, a first detection unit which is disposed above the table to detect an optical signal from the substrate, a second detection unit which is disposed above the table to detect an electrical signal from the substrate, and a signal processing unit which is connected to the first detection unit and the second detection unit to detect a chemical defect using the optical signal and the electrical signal.

Defect inspection apparatus and defect inspection method using the same

A method of measuring a step height of a device using a scanning electron microscope (SEM), the method may include providing a device which comprises a first region and a second region, wherein a step is formed between the first region and the second region, obtaining a SEM image of the device by photographing the device using a SEM, wherein the SEM image comprises a first SEM image region for the first region and a second SEM image region for the second region, converting the SEM image into a gray-level histogram and calculating a first peak value related to the first SEM image region and a second peak value related to the second SEM image region, wherein the first peak value and the second peak value are repeatedly calculated by varying a focal length of the SEM, and determining a height of the step by analyzing a trend of changes in the first peak value according to changes in the focal length and a trend of changes in the second peak value according to the changes in the focal length.

Method and apparatus to measure step height of device using scanning electron microscope

In a method of generating a three-dimensional process window qualification, a photoresist layer is coated on a substrate including an underlying structure. A plurality of circular-shaped regions of the substrate are distinguished into 1 to n regions to partition the substrate into a center portion and an edge portion, n being a natural number greater than 2. 1 to n exposing ranges are set, including a common exposing condition for the 1 to n regions. A photoresist pattern is fox led by exposing each shot portion in the 1 to n regions using a split exposing condition in the 1 to n exposing ranges. The photoresist pattern is detected, and a normal photoresist pattern with respect to each of the 1 to n regions is selected to generate the three-dimensional process window qualification.

Methods of generating three-dimensional process window qualification

A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode.

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Seongnam-si, South Korea

Young-Hoon Sohn