International Business Machines Corporation

Other

Young Hoon Lee

Kevin K Chan

Sang Hoo Dhong

Hussein Ibrahim Hanafi

Dieter P Kern

Ying Di Zhang

Keith Raymond Milkove

John William Stiebritz, Jr

In at least one embodiment, there is a nail polish applicator for nail polish, the applicator comprising: a container body, at least one cap or lid body which is coupled to the container body. There is at least one brush comprising a shaft coupled to the cap wherein the shaft has a storage body disposed therein. There is at least one air suction unit configured to draw nail polish into the storage body. There is also a compressor comprising an elastic pressing body configured to compress the air suction unit to draw nail polish into the storage body. The compressor is coupled to the cap. The compressor comprises at least one protrusion and at least one leaf spring coupled to the cap, such that when the protrusion is pressed, it compresses the suction unit to draw nail polish into the storage body.

Nail polish container

Scissor tweezer

In a dual-damascene processes for multi level interconnection a method for forming trenches and vias in the inter-insulation is accomplished without etching out the inter-insulation layer. A thick sacrificial layer is first deposited and reversed etched to form sacrificial pillars 64 forming the vias and sacrificial bridges 72 forming the trenches. The sacrificial layer can be any material (insulator, semiconductor, or metal), provided it can be easily patterned and selectively removed later over the inter insulator layer. Thereafter a low-k inter-insulation layer is deposited around the sacrificial pillars and bridges. It is these sacrificial pillars and bridges that are etched away leaving behind vias and trenches in the inter-insulation layer. An advantage of the invention is that it replaces a difficult RIE process of vias and trenches with a much easier RIE of sacrificial pillars and bridges. In the preferred embodiment, a silicon film, either amorphous or polycrystalline, is used as the sacrificial layer.

Method for forming vias and trenches in an insulation layer for a

The present invention relates to a recessed channel/gate MOSFET structure which comprises a semiconductor wafer having a plurality of shallow trench isolation regions embedded therein, wherein between each adjacent shallow trench isolation region is a field effect transistor region which comprises a source and drain region which are spaced apart by a gate region, said gate region comprising a poly gate region which is positioned between oxide spacers, said poly gate region having a metal contact region on its top surface and a gate oxide region on its bottom surface embedded in said semiconductor wafer and wherein said source and drain regions have an extension which wraps around said oxide spacers and provides a connection with a channel region which is formed below said gate oxide region.

Recessed-gate MOSFET with out-diffused source/drain extension

The present invention provides a process of fabricating high aspect ratio holes (H/L is 2 or greater) in a semiconductor structure wherein a masked gate-like reactive ion etch process is employed. The high aspect ratio holes have perfectly vertical sidewalls thus they are particularly useful in fabricating gate electrodes of sub-0.05 .mu.m MOSFETs using a damascene process.

Methods for making high-aspect ratio holes in semiconductor and its

A method for etching silicon is described incorporating first and second steps of reactive ion etching through a patterned oxide layer in respective atmospheres of HBr, Cl.sub.2 and O.sub.2 and then HBr and O.sub.2 in situ by terminating the first etching step and removing substantially all Cl.sub.2 before continuing with the second step of etching. The invention overcomes the problem of uneven etching of n+ and p+ silicon gates for CMOS transistor logic during the step of simultaneously etching silicon to form sub 0.25 micron gate lengths and vertical sidewalls while stopping on the gate oxide.

Silicon etching method

A plasma reactor and method for forming a dense plasma from a gas is described incorporating a housing, a gas inlet to the housing, a pump for evacuating the housing, a magnetic coil to generate a magnetic field in the housing, a radio frequency power supply, an electrode or induction coil in the housing, a microwave power supply. The invention overcomes the problem of an upper plasma density limit independent of increases in microwave power.

Plasma reactor for processing substrates

A flash EEPROM is produced comprising multiple MOS cells. In each cell, programming and erasing are performed through tunneling from the write gate to the floating gate and by tunneling from the floating gate to the erase gate, respectively. The directional dielectric employed is a multilayered structured (MLS) oxide, where thin oxide and thin polycrystalline silicon form alternating layers. The layering is asymmetric: that is, either the uppermost or bottommost layer is thicker than the other layers. As a result of this structure, the oxide exhibits directionality, that is, the tunneling is easier in one direction than the reverse direction, and significantly enhances the tunneling phenomena (tunneling current can be observed at as low as 4.7 V). In addition, the MLS oxide can be fabricated having different dielectric constants. The directionality, coupled with the separate write and erase gates, gives the new flash EEPROM cell a number of advantages: it is low-voltage operable, it is highly resistant to disturbance and has an easily scalable structure (that is, it can be made to operate at any given voltage within a specified scale).

Method for manufacturing a memory cell

Asymmetric multilayered dielectric material and a flash EEPROM using the

A plasma reactor for forming a dense plasma from a gas is described incorporating a housing, a gas inlet to the housing, a pump for evacuating the housing, a magnetic coil to generate a magnetic field in the housing, a radio frequency power supply, an electrode or induction coil in the housing, a microwave power supply. The invention overcomes the problem of an upper plasma density limit independent of increases in microwave power by inducing electron cyclotron resonance (ECR) and ion cyclotron resonance (ICR) conditions.

Growing community of inventors

Somers, NY, United States of America

Young Hoon Lee