Samsung Electronics Co., Ltd.

Skhynix Inc.

Seoul National University

Industry-University Cooperation Foundation Hanyang University

Dongwoo Fine-Chem Co., Ltd.

Other

Lg Display Co., Ltd.

Korea Advanced Institute of Science and Technology

Alliance for Sustainable Energy, LLC

Cj Corporation

Toolgen Inc.

Electronics and Telecommunications Research Institute

Lg Chem, Ltd

Young-Hoon Kim

Sungjin Kim

Dong-Myung Kim

Jin Woo Park

Seung-Chan Bang

Young-Jo Ko

Kapseok Chang

Tae-Woo Lee

Sun-Tae Jung

Ki-Woong Kim

Sung-Jin Kwon

Chun-Seok Jeong

Il-Gyu Kim

Soon-Ho Ahn

Dong-Kyoon Han

Su-Yeon Oh

In-Ho Lee

Hyeong-Geun Park

Chang-Sik Yoo

Kang-Seol Lee

Soo-suk Lee

Byeong-Soo Bae

Nam-Jong Kim

Seung-Min Ryu

Nam-Hea Jang

Joseph Jonathan Berry

Soo-Young Jang

Joseph Matthew Luther

In-jae Lee

Seokjoong Kim

Jang-seok Ma

Haeng-soo Lee

Young-nam Kwon

Jun-hwan Lee

Seung Pil Han

Nam-young Jang

Ji-Hoon Han

Min Hee Jung

Fu Wang

Min Ju Lee

Haipeng Lu

Jeong Min Choi

Young-hwan Lee

Jun-Ho Jang

Yaxin Zhai

Himchan Cho

Hui-jun Sim

Hyung-Seok Seo

Tae-jin Ham

Seong-woo Kang

Kang In Lee

Jin-ah Kang

Jeongjoon Lee

Eunji Shin

Joonsun Lee

Seong-hak Jeong

Hi-jae Cho

Hee-chol Kang

Described herein are spin polarized light emitting diodes (LEDs) and methods of making the same. Spin polarization is achieved via chiral induced spin selectivity where, for example, a stereochemically active cation is included in a perovskite to form the conductive layer of an LED device. Advantageously, the devices and methods described herein allow for spin polarization at room temperature and without application of a magnetic field or ferromagnetic contacts, in contrast to other described spin selective LEDs.

Chiral induced spin selectivity enabling a room temperature spin polarized light emitting diode

The present invention relates to a light emitting device including a light emitting layer having a stacked structure of two or more layers in which the light emitting layer is alternately disposed with a first light emitting material layer and a second light emitting material layer. In addition, the light-emitting material layer is a perovskite layer or an organic material layer, the first light-emitting material layer and the second light-emitting material layer are characterized in that they have different band gaps. By alternately disposing the first light emitting material layer and the second light emitting material layer to have a stacked structure and by controlling the energy level, there is an advantage in that the electroluminescence efficiency can be improved by controlling the electron-hole recombination region of the light emitting device. In addition, there is an advantage that a white light emitting device can be manufactured by controlling the energy levels of the first light emitting material layer and the second light emitting material layer.

Light-emitting diode comprising perovskite light-emitting layer having layered structure, and method of producing same

Disclosed is a perovskite light-emitting device with reduced defects in a perovskite thin film. The passivation layer in the perovskite light-emitting device is formed on the upper part of the perovskite thin film to eliminate defects in the perovskite nanocrystalline particles and resolve charge imbalance in the device, thereby improving maximum efficiency and maximum luminance of the light-emitting device.

Perovskite light-emitting device having passivation layer and fabrication method thereof

Disclosed are a perovskite color converter and a method for manufacturing the same. In order to maintain strong physical properties, the siloxane resin is synthesized in two steps. The silane precursor performs siloxane bond through a non-aqueous sol-gel reaction to form a siloxane resin, and a bond between methacrylate group, and a bond between methacrylate group and an organic ligand are formed through a secondary cross-linking reaction.

Perovskite color converter and method of manufacturing the same

Particle measurement device

Disclosed are a light emitting device including a perovskite charge transport layer and a method of manufacturing the same. Perovskite thin film of the light emitting device is prepared by co-depositing or sequentially depositing perovskite precursors. Perovskite is directly deposited on the substrate, the thickness of the perovskite thin film is easily controlled, and the energy level is easily adjusted. So, a charge transport layer functioning as a hole injection layer or an electron injection layer in the light emitting device may be manufactured to have suitable energy level.

Light emitting device comprising perovskite charge transport layer and manufacturing method thereof

The present disclosure relates to a DRD type display panel. The display panel includes first to fourth pixels; a first data line through which a data signal is transmitted to the first and second pixels; a second data line through which a data signal is transmitted to the third and fourth pixels; a first gate line through which a scan signal is transmitted to the first and third pixels; a second gate line through which a scan signal is transmitted to the second and fourth pixels; a reference voltage line used to detect deterioration of OLEDs in the first to fourth pixels; a first power line positioned on the left of the first data line and supplying driving power to the first and second pixels; and a second power line positioned on the right of the second data line and supplying driving power to the first and second pixels.

DRD type display panel and organic light emitting display device using same

A semiconductor device includes a substrate provided with a decoupling capacitor and plurality of circuit elements disposed along a first direction, and a plurality of first wiring line patterns disposed in a first wiring line layer over the substrate, including a power routing pattern coupled to the decoupling capacitor and a plurality of internal wiring line patterns coupled to the plurality of circuit elements. The plurality of first wiring line patterns extend in the first direction, and are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting the first direction and parallel to the substrate.

Semiconductor device

Plasma monitoring flow cell

The present invention relates to an artificially engineered CRISPR/Cas9 system. More particularly, the present invention relates to an artificially engineered CRISPR enzyme having enhanced target specificity and a use of an artificially engineered CRISPR/Cas9 system including the same enzyme in genome and/or epigenome manipulation or modification, genome targeting, genome editing, and in vitro diagnosis, etc.

Target-specific CRISPR mutant

A semiconductor device that includes active patterns defined in a substrate, and gate patterns extending in a first direction while traversing the active patterns. First wiring line patterns disposed over a first dielectric layer which covers the gate patterns, and extending in the first direction. The first wiring line patterns comprise internal wiring line patterns coupled with first vertical vias, which pass through the first dielectric layer and are coupled to the active patterns and the gate patterns, and power routing patterns not coupled with the first vertical vias. The first wiring line patterns are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting with the first direction, and the first active patterns are disposed between the power routing patterns when viewed on a top.

A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.

Phase detector, phase-frequency detector, and digital phase locked loop

A signal transmission circ it includes a main driving unit configured to drive a first signal transmission One in response to an input signal and output a first driven signal, an emphasis driving unit configured to perform an emphasis operation on the first driven signal and output an emphasized signal, and a crosstalk control unit configured to perform an equalizing operation on the emphasized signal.

Signal transmission circuit

Digital image photographing apparatuses and methods of controlling the same to provide location information are disclosed. A disclosed example method includes generating a preview image by photographing an object; detecting the current location of the digital image photographing apparatus; detecting a photographing direction in which the digital image photographing apparatus photographed the object; generating distance information regarding the object; and displaying the distance information regarding the object according to the photographing direction around the current location of the digital image photographing apparatus. Digital image photographing apparatuses disclosed herein are capable of providing location information and/or additional information regardless of its their optical limits.

Digital image photographing apparatuses and methods of controlling the same to provide location information

An internal voltage generator circuit is disclosed. The internal voltage generator circuit includes a comparator configured to compare a first voltage with a reference voltage and to output a comparison signal. The circuit further includes an internal voltage driver configured to receive an external voltage and the comparison signal and to output an internal voltage at an internal voltage output terminal, based on the comparison signal. The circuit further includes a voltage divider circuit including first and second resistor units and a first voltage output terminal between the first and second resistor units, configured to receive the internal voltage, and configured to output the first voltage based on the resistance values of the first and second resistor units, the first and second resistor units connected in series, and the first voltage being output through the first voltage output terminal. The circuit further includes a control signal generator circuit configured to generate at least one resistor control signal for controlling the resistance value of the first resistor unit and at least one resistor control signal for controlling the resistance value of the second resistor unit, on the basis of the comparison signal and a precharge command.

Internal voltage generator circuit and semiconductor memory device using the same

Growing community of inventors

Seoul, South Korea

Young-Hoon Kim