Samsung Electronics Co., Ltd.

Young-Ho Suh

Kyo-Min Sohn

Choong-Keun Kwak

Du-Eung Kim

Byung-Gil Choi

Sang-Jib Han

Hyun-Geun Byun

Suk-Bin Kim

Jin-Ho Lee

Dae-Yong Kim

Chul-Min Jung

Soo-Hwan Kim

Yong-Hwan Noh

Kook-Hwan Kwon

Hyo-Yun Nam

Choung-Keun Kwak

A semiconductor memory device which a pad for receiving a power voltage, a first power line connected to the pad, and a plurality of second power lines respectively connected to memory cells of a repair unit. A selection circuit outputs selection signals for selecting the memory cells of the array in the repair unit in response to a row address in a test operation mode. A power switch circuit operates in response to the selection signals, and connects the second power line connected to the selected memory cells with the first power line in the test operation mode. The power switch circuit disconnects the remaining second power lines from the first power line.

Semiconductor memory device with standby current failure judging function and method for judging standby current failure

A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit line comprising a bit line pair.

Layout structures in semiconductor memory devices including bit line layout for higher density migration

An integrated circuit comprising a memory cell array capable of simultaneously performing data read and write operations is provided. The integrated circuit to which inputs and outputs (IOs) are separately provided and to which a write address and a read address are simultaneously input during one period of a clock signal comprises a plurality of memory blocks, the memory blocks comprising a plurality of sub-memory blocks, a plurality of data memory blocks corresponding to the memory blocks, and a tag memory controlling unit, which writes data to the memory blocks or reads data from the memory blocks in response to the write address or the read address, wherein access to the same sub-memory block is not simultaneously performed when the write address and the read address are the same.

Integrated circuit having a memory cell array capable of simultaneously performing a data read operation and a data write operation

Memory devices are provided which are capable of performing burst operations by simultaneously writing/reading a plurality of data bits to/from memory in response to a selection of a single wordline, and which are capable of controlling data input/output for interruption of burst operation interruptions without having to employ complex control circuitry.

SRAM device capable of performing burst operation

A semiconductor memory device and a method of operating the semiconductor memory device are disclosed. The semiconductor memory device comprises a memory cell array having a plurality of cell array blocks. The cell array blocks are operationally divided into a plurality of memory planes using a memory determining unit. Each of the memory planes comprises at least one cell array block and is capable of executing independent data access operations using an independent operating mode.

Semiconductor memory device having memory architecture supporting hyper-threading operation in host system

A column select circuit in a Static Random Access Memory (SRAM) having a three-dimensional layout can include a lower CMOS layer in a substrate and an upper NMOS layer above the lower layer. An intermediate PMOS layer is located between the upper NMOS layer and the lower CMOS layer.

3-D column select circuit layout in semiconductor memory devices

A method of controlling an integrated circuit (IC) capable of simultaneously performing a data read operation and a data write operation is provided. The method comprises (a) receiving a write address, a read address, and write data, (b) determining, a memory block and a data memory block in which a data read operation and a data write operation are to be performed in response to the write address and the read address, (c) performing the data read operation or the data write operation in the data memory block according to the determination of step (b), and (d) performing the data read operation or the data write operation in the memory block according to the determination of step (b).

Method of controlling an integrated circuit capable of simultaneously performing a data read operation and a data write operation

Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin-film transistors. These thin-film transistors include a first PMOS thin-film pull-up transistor and a first NMOS thin-film pass transistor. These thin-film transistors are electrically coupled to one of the first pair of bit lines. The first column of memory cells includes a column of TFT SRAM cells.

Integrated circuit memory devices having hierarchical bit line selection circuits therein

An integrated circuit and a method of reading and writing data at the same time are provided. The integrated circuit has separate input and output ports and a write address and a read address are input during a period of a clock signal. The circuit includes memory blocks that respectively include a plurality of sub memory blocks, cache memory blocks that respectively correspond to the memory blocks, and a tag memory control unit. The tag memory control unit controls reading data from and writing data to the memory blocks and the cache memory blocks in response to the write address or the read address. In particular, reads of the data from or writes of the data to the memory block and the cache memory block at the same time are performed if an upper address of the read address and an upper address of the write address are identical to each other. Since data can be separately read from and written to a memory block or a cache memory block at the same time during a period of a clock signal, an operational frequency of the clock signal can be increased.

Method and integrated circuit capable of reading and writing data simultaneously

Methods and apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus. Read and write operations are sequentially performed in a same cycle using QDR2 (Quadruple Data Rate 2) wherein each of the input and output modes operate at a 2-bit burst mode and a double data rate (DDR) mode, thereby minimizing cycle time or read and write operations are sequentially performed in a same cycle using QDR4 (Quadruple Data Rate 4), wherein each of the input and output modes operate at a 4-bit burst mode and a DDR mode, thereby minimizing the cycle time. In another aspect, when a read command is input in one cycle, a read operation is performed in synchronization with a rising edge of clock and a write operation is performed in synchronization with a signal that operates during the read operation.

Method and apparatus for read operation and write operation in semiconductor memory device

A semiconductor memory device having redundancy with no performance penalty. The semiconductor memory device with redundancy includes a default array; a row redundant array block separated from the default array and provided with row redundant arrays for making up for a deficiency in a row direction; a column redundant array block separated from the default array and provided with column redundant arrays for making up for a deficiency in a column; a control block supplying a control signal commonly to the default array, row redundant array, and column redundant array; and a redundant calculation block for receiving address and control signals to generate a control signal necessary to the redundant array and to determine whether the redundant array is accessed, and to generate a signal to disable a sense amplifier of the default array during the redundant array access.

Semiconductor memory device with redundancy

A data output circuit for a semiconductor device with a level shifter and a method for outputting data using the same. The data output circuit comprises an output buffer for receiving and latching an input data signal with a first voltage range in response to a clock control signal to provide a pair of output data signals, a high-impedance controller/level shifter circuit for outputting high-impedance drive data for the control of a high-impedance state through a pair of output lines according to a first logic state of a high-impedance control signal and for receiving the output data signal pair from the output buffer according to a second logic state of the high-impedance control signal and transferring pull-up and pull-down output data signals with a second voltage range through the output lines, and an output driver for maintaining a data output terminal at the high impedance state in response to the high-impedance drive data from the high-impedance controller/level shifter circuit and for performing an output driving operation in response to the pull-up and pull-down output data signals from the high-impedance controller/level shifter circuit to output final data externally through the data output terminal. A data output speed and a high-impedance transition speed are improved and an excellent driving capability is obtained.

Data output circuit for semiconductor device with level shifter and method for outputting data using the same

In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.

High-speed synchronous semiconductor memory having multi-stage pipeline structure and operating method

A data transmission circuit is provided for compensating for a difference between data transmission speed occurring at start and end portions of a data line. The circuit minimizes a time delay caused by resistance/capacitance loading of the data line through which data is transmitted, thereby improving data transmission speed. The data transmission circuit of the present invention includes a compensation circuit to compensate for the time delay between the data signals at the start and end portions of the data line. The compensation circuit is adapted to amplify and rapidly develop a data signal at the end portion of the data line through which a data signal is enabled from its high state to its low state and transmitted as a data signal at the end portion of the data line.

Data transmission circuit for compensating difference of speed

A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

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Suwon-si, South Korea

Young-Ho Suh