Samsung Electronics Co., Ltd.

Young-Ho Lim

Dong-Hyuk Chae

Dae-Seok Byeon

Sang-gu Kang

Sung-Soo Lee

Moo-sung Kim

Hyun-Chul Cho

Kang-Deog Suh

Seung-Keun Lee

Dong-Ku Kang

Yeong-taek Lee

Jae-Yong Jeong

June Hyung Lee

Ki-Hwan Choi

Chang-Hyun Lee

Jung-Dal Choi

Seung-Jae Lee

Sang-Wan Nam

Jung-Hoon Park

Dae-seok Byeon

Byeong-Hoon Lee

Sung-soo Lee

Dae-Han Kim

Byeng-Sun Choi

Jae-Woo Im

Soo-Hwan Choi

Tae-Hee Cho

Ki-Tae Park

Chang-Sub Lee

Jong-wook Park

Heung-Soo Im

Hwi-Taek Chung

Wook-Ghee Hahn

Hyoung-Gon Kim

Sun-Mi Choi

Byeng-Soon Choi

Ki-hwan Choi

Wook-Ghee Han

Myung-Jae Kim

Eung-Moon Yeon

Beyng-Sun Choi

A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.

Nonvolatile semiconductor memory device with advanced multi-page program operation

Provided is a method of storing configuration data regarding an operating environment of a flash memory device, which includes a memory cell array having an electrical fuse (E-Fuse) block for storing the configuration data. The method includes storing the configuration data in multiple strings of the E-Fuse block, each string including multiple memory cells configured to store one bit.

Method of storing E-fuse data in flash memory device

A non-volatile memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path.

Page-buffer and non-volatile semiconductor memory including page buffer

Disclosed is a flash memory device having multiple strings, where each string includes first memory cells and second memory cells. One second memory cell of the second memory cells in each string is set to a programmed state, and remaining second memory cells are set to an erased state.

Flash memory device having dummy cells and method of operating the same

In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages.

Flash memory device and program recovery method thereof

A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.

Flash memory device and program method of flash memory device using different voltages

Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing even-numbered nonvolatile memory cells in the first string and then selectively erasing the odd-numbered nonvolatile memory cells in the first string, which may be interleaved with the even-numbered nonvolatile memory cells. This operation to selectively erase the even-numbered nonvolatile memory cells may include erasing the even-numbered nonvolatile memory cells while simultaneously biasing the odd-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the odd-numbered nonvolatile memory cells. The operation to selectively erase the odd-numbered nonvolatile memory cells may include erasing the odd-numbered nonvolatile memory cells while simultaneously biasing the even-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the even-numbered nonvolatile memory cells.

Methods of operating nonvolatile memory devices to inhibit parasitic charge accumulation therein

A nonvolatile semiconductor memory device for an efficient program of multilevel data includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks. Accordingly, the time taken in programming can be reduced without increasing a unit of program in a multilevel flash memory, thereby improving performance in a multilevel program of a nonvolatile semiconductor memory device.

A non-volatile memory device and related method of driving data are disclosed. The non-volatile memory device includes an array of multi level cells and a monitoring memory cell. The method of driving including performing a preliminary read operation with respect to a monitoring memory cell using a first read voltage, determining whether data initially stored in the monitoring memory cell is identical with data read from the monitoring memory cell during the preliminary read operation, and setting a main read voltage to a level different from the level of the first read voltage when the data initially stored in the monitoring memory cell is not identical with the data read from the monitoring memory cell in relation to the first read voltage.

Non-volatile memory device having monitoring memory cell and related method of driving using variable read voltage

A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.

Flash memory device and method of controlling flash memory device

Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.

Methods and circuits for generating a high voltage and related semiconductor memory devices

Provided is a method for programming a flash memory device. The method includes receiving writing data, detecting leakage bit lines of the flash memory device, and updating the received writing data in order for data corresponding to the leakage bit lines to be modified as program-inhibit data. A programming operation is performed on the flash memory device after updating the writing data.

Flash memory device and method for programming flash memory device having leakage bit lines

A flash memory device includes a cell array and a decision unit. The cell array includes multiple regions corresponding to multiple input/output lines. Initialization data are repeatedly stored in each of the regions. The decision unit determines whether the stored data are valid based on values of bits of the stored data read from each region.

Growing community of inventors

Yongin-si, South Korea

Young-Ho Lim