International Business Machines Corporation

Globalfoundries Inc.

Young-Hee Kim

Dae-Gyu Park

Kevin K Chan

Effendi Leobandung

Jack Oon Chu

Cheng-Wei Cheng

Min Yang

Bruce Bennett Doris

Vijay Narayanan

Eduard Albert Cartier

Pranita Kerber

Vamsi Krishna Paruchuri

Ying Di Zhang

Isaac Lauer

Martin Michael Frank

Ramachandran Muralidhar

Huiming Bu

Deborah A Neumayer

Devendra K Sadana

Takashi Ando

Theodorus E Standaert

Ali Afzali-Ardakani

Keith Kwong Hon Wong

Solomon Assefa

Barry P Linder

Cyril Cabral, Jr

Fei Liu

Kenneth Parker Rodbell

Jeng-Bang Yau

Laertis Economikos

Dirk Pfeiffer

Jeffrey Curtis Hedrick

Yurii A Vlasov

Matthew Warren Copel

Masaharu Kobayashi

Harold John Hovel

Xinhui Wang

Yanning Sun

Qiang Huang

Jinghong Li

William M Green

Satyavolu S Papa Rao

Michelle Leigh Steen

Uzma B Rana

Joris Van Campenhout

George Gabriel Totir

Kathryn C Fisher

Marinus J P Hopstaken

Tsong-Lin Tai

Susan Huang

James N Pan

Mahmoud M Khojasteh

Kenneth Jay Stein

William J Cote

Gregory M Fritz

Christopher Peter D'Emic

Christopher V Baiocco

Changhwan Choi

Helen Wang

Jun Liu

Yurri A Vlasov

Ys Suh

Elizabeth A Duch

Rajarao c/o Ibm United Kingdom Ltd Jammy

Bruce B Ibm United Kingdom Ltd Doris

A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.

Reduced current leakage semiconductor device

A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.

Fin field effect transistor including a strained epitaxial semiconductor shell

An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Selective dopant junction for a group III-V semiconductor device

An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300&#xb0; C. and 750&#xb0; C. The dopant layer includes at least 4&#xd7;10active dopant atoms per cmthat react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.

FinFET field-effect transistors with atomic layer doping

A stack of a germanium-containing layer and a dielectric cap layer is formed on an insulator layer. The stack is patterned to form germanium-containing semiconductor fins and germanium-containing mandrel structures with dielectric cap structures thereupon. A dielectric masking layer is deposited and patterned to mask the germanium-containing semiconductor fins, while physically exposing sidewalls of the germanium-containing mandrel structures. A ring-shaped compound semiconductor fin is formed around each germanium-containing mandrel structure by selective epitaxy of a compound semiconductor material. A center portion of each germanium-containing mandrel can be removed to physically expose inner sidewalls of the ring-shaped compound semiconductor fin. A high-mobility compound semiconductor layer can be formed on physically exposed surfaces of the ring-shaped compound semiconductor fin. The dielectric masking layer and fin cap dielectrics can removed to provide germanium-containing semiconductor fins and compound semiconductor fins.

Integration of Ge-containing fins and compound semiconductor fins

Fabrication of field-effect transistors with atomic layer doping

Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

Process variability tolerant hard mask for replacement metal gate finFET devices

A stack of a first anti-reflective coating (ARC) layer and a titanium layer is formed on a front surface of a semiconductor substrate including a p-n junction, and is subsequently patterned so that a semiconductor surface is physically exposed in metal contact regions of the front surface of the semiconductor substrate. The remaining portion of the titanium layer is converted into a titania layer by oxidation. A metal layer is plated on the metal contact regions, and a copper line is subsequently plated on the metal layer or a metal semiconductor alloy derived from the metal layer. A second ARC layer is deposited over the titania layer and the copper line, and is subsequently patterned to provide electrical contact to the copper line.

Integration of a titania layer in an anti-reflective coating

The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell. When the at least one photovoltaic cell is exposed to radiation, the at least one photovoltaic cell generates a current that causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and a reactive material coupled to the at least one photovoltaic cell, wherein a current from the at least one photovoltaic cell triggers an exothermic reaction in the reactive material.

Integrated circuit tamper detection and response

Growing community of inventors

Mohegan Lake, NY, United States of America

Young-Hee Kim