Lg Semicon Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Young Gwan Kim

Jeong Hwan Son

Jae Gyung Ahn

Hyun Kyu Han

Myoung Goo Lee

A method for fabricating a semiconductor device in which channel resistance is prevented from occurring due to impurity ion diffusion and gate resistance is reduced, thereby improving the speed characteristic of the device. The method for forming a dual gate of a semiconductor device includes the steps of forming a polysilicon layer on a semiconductor substrate; selectively forming an impurity ion layer of a first conductive type and an impurity ion layer of a second conductive type on a lower surface to the polysilicon layer; polishing the polysilicon layer; forming a low resistance metal layer on the polished polysilicon layer; forming a first gate electrode and a second gate electrode by an etching process using a gate mask; and forming source/drain regions of the first conductive type in the substrate at both sides of the first gate electrode and source/drain regions of the second conductive type in the substrate at both sides of the second gate electrode.

Method for fabricating semiconductor device

Semiconductor device and method for fabricating the same, is disclosed, which can maintain a threshold voltage constant despite of decreased channel width, the device including a first, and a second conductive type wells in a substrate, a first, and a second gate insulating films on the first, and the second conductive type wells, a first gate electrode on the first gate insulating film, the first gate electrode being doped with a second conductive type except for edges of the first gate electrode in a channel width direction counter doped with a first conductive type, a second gate electrode on the second gate insulating film, the second gate electrode being doped with a first conductive type except for edges of the second gate electrode in a channel width direction counter doped with a second conductive type, and isolating regions formed between the first, and second conductive type wells, the first, and second gate insulating films, and the first, and second gate electrodes.

Method of making semiconductor device with decreased channel width and

An ESD (Electro-Static Discharge) protection circuit includes a semiconductor substrate having an active region and field regions, isolating films formed in the field regions, a gate insulating film formed on the active region, and a gate electrode formed on the gate insulating film, first and second heavily doped impurity regions formed in a surface of the semiconductor substrate at sides of the gate electrode, a plurality of dummy gate electrodes formed on the second heavily doped impurity region and offset from the gate electrode, insulating sidewalls formed at the sides of the gate electrode and at sides of each of the dummy gate electrodes, and salicide films formed on a surface of the gate electrode, on surfaces of each of the dummy gate electrodes and on a surface of the first heavily doped impurity region.

ESD protection circuit and method for fabricating same using a plurality

A method of fabricating a phase inverted mask comprising the steps of forming a shielding layer pattern on a substrate, injecting oxygen ions into a surface of the shielding layer pattern, and converting the shielding layer pattern having the oxygen ions injected therein into an oxidation layer to thereby form a phase inverted layer.

Growing community of inventors

Chungcheongbuk-do, South Korea

Young Gwan Kim