Samsung Electronics Co., Ltd.

Leland Stanford Junior University

Young-gu Jin

Young-chan Kim

Tae-sub Jung

Yoon-Dong Park

Jong-seob Kim

Sung-il Park

Jae-woong Hyun

Sung-hoon Lee

Jai-kwang Shin

Seung-hoon Lee

Ki-ha Hong

Eun-kyung Lee

Jun-young Kim

Chang-rok Moon

In-sung Joe

Pil-soo Ahn

Byoung-Iyong Choi

Yong-hun Kwon

Sung-Ho Choi

Suk-Pil Kim

Won-Joo Kim

Seok-soo Lee

Kwang-Soo Seol

Won-joo Kim

Bok-ki Min

Min-Sun Keel

Young-sin Park

Yoon-dong Park

Dae-Kil Cha

David Andrew Barclay Miller

A 3D image sensor include a depth pixel and at least two polarization pixels adjacent to the depth pixel. The depth pixel includes a charge generation region in a substrate. The depth pixel is configured to generate depth information associated with a depth of an object from the 3D image sensor in a 3D scene based on detecting light reflected from the object. Each polarization pixel includes a photodiode in the substrate and a polarizer on the substrate in a light-incident direction. The polarization pixel is configured to generate shape information associated with a shape of a surface of the object in the 3D scene based on detecting light reflected from the object. The polarization pixels and the depth pixel collectively define a unit pixel. The respective polarizers are associated with different polarization directions.

Three-dimensional (3D) image sensors including polarizer, and depth correction methods and 3D image generation methods based on 3D image sensors

An image sensor includes a semiconductor substrate including a first surface and a second surface and further includes a well region and a first floating diffusion region that are each adjacent to the first surface. The image sensor includes a first vertical transmission gate and a second vertical transmission gate isolated from direct contact with each other and each extend from the first surface of the semiconductor substrate and in a thickness direction of the semiconductor substrate through at least a portion of the well region. The image sensor includes a first storage gate between the first vertical transmission gate and the first floating diffusion region and on the first surface of the semiconductor substrate. The image sensor includes a first tap transmission gate between the first storage gate and the first floating diffusion region and on the first surface of the semiconductor substrate.

Image sensors for distance measurement

A Time-of-Flight (ToF)-based three-dimensional (3D) image sensor includes at least two first photogates symmetrically arranged in a central portion of a pixel, at least two first gates configured to remove an overflow charge generated in the at least two first photogates, and a first gate group. The at least two first gates are arranged symmetrically in an outer portion of the pixel. The first gate group includes a plurality of gates configured to store and transmit charges generated in the at least two first photogates. The first gate group is arranged in the outer portion of the pixel.

Three-dimensional image sensor based on time of flight and electronic apparatus including the image sensor

A pixel array in a three-dimensional image sensor includes depth pixels and an ambient light cancellation (ALC) circuit. The depth pixels operate in response to photo control signals having different phases, and generate distance information of an object based on light reflected by the object. The ALC circuit removes an ambient light component from the reflected light, and is shared by the depth pixels. Each depth pixel includes a photoelectric conversion region, a floating diffusion region, a photo gate, and a drain gate. The photoelectric conversion region collects photo charges based on the reflected light. The floating diffusion region accumulates the photo charges. The photo gate is activated in response to one of the photo control signals. The photoelectric conversion region accumulates the photo charges when the photo gate is activated, and the photo charges in the photoelectric conversion region are released when the drain gate is activated.

Pixel array included in three-dimensional image sensor and method of operating three-dimensional image sensor

An image sensor including a light source configured to emit an optical signal to a target object, and a pixel array including a first pixel configured to generate pixel signals based on the optical signal reflected from the target object, the first pixel including a first photo gate group having at least two photo gates that are configured to receive first gate signals with a first phase difference from the optical signal in a time interval and a second photo gate group having at least two photo gates configured to receive second gate signals with a second phase difference from the optical signal in the time interval, may be provided.

Image sensor and image processing system having pixel structure to improve demodulation contrast performance

An image sensor includes unit pixels, and from among the unit pixels, a first unit pixel and a second unit pixel that are adjacent to each other each include a first tap having a first photo gate, to which a first signal having a first phase difference with respect to an optical signal is applied, and a second tap having a second photo gate, to which a second signal having a second phase difference with respect to the optical signal is applied. A location of the first tap in the first unit pixel and a location of the first tap in the second unit pixel, and a location of the second tap in the first unit pixel and a location of the second tap in the second unit pixel are symmetrical with each other based on one point between the first unit pixel and the second unit pixel.

Image sensor including multi-tap pixel

The image sensor includes: a semiconductor substrate having a first conductivity type and including a first surface, a second surface opposite to the first surface, and a well region adjacent to the first surface. A first vertical transfer gate and a second vertical transfer gate are spaced apart from each other and extend in a thickness direction of the semiconductor substrate from the first surface to pass through at least a part of the well region. A photoelectric conversion region has a second conductivity type, which is different from the first conductivity type, is located in the semiconductor substrate between the well region and the second surface, and overlaps the first vertical transfer gate and the second vertical transfer gate in the thickness direction of the semiconductor substrate. A wiring structure is located on the first surface of the semiconductor substrate.

Image sensor for measuring distance

Silicon photodetectors using near-infrared dipole antennas. The photodetectors include a silicon region formed on a semiconductor substrate, dipole antenna forming two arms that are spaced apart with the silicon region therebetween and inducing an electromagnetic wave signal of incident light, and electrodes disposed in a vertical direction of the dipole antenna and spaced apart with the silicon region therebetween, where a critical bias voltage is applied to the electrodes to induce an avalanche gain operation in the silicon region.

Near-infrared photodetectors, image sensors employing the same, and methods of manufacturing the same

An image sensor includes a plurality of unit pixels arranged in an array. Each unit pixel includes a plurality of sub-pixels configured to be irradiated by light having the same wavelength. Each sub-pixel includes a plurality of floating body transistors. Each floating body transistor includes a source region, a drain region, a floating body region between the source region and the drain region, and a gate electrode formed on the floating body region.

Sub-pixels, unit pixels, image sensors and methods of operating the same

Provided is a method of reliably operating a highly integratable nonvolatile memory device. The nonvolatile memory device may include a string selection transistor, a plurality of memory transistors, and a ground selection transistor between a bit line and a common source line. In the nonvolatile memory device, data may be erased from the memory transistors by applying an erasing voltage to the bit line or the common source line.

Nonvolatile memory device and method of operating and fabricating the same

Provided are a non-volatile memory device that may expand to a stacked structure and may be more easily highly integrated and an economical method of fabricating the non-volatile memory device. The non-volatile memory device may include at least one semiconductor column. At least one first control gate electrode may be arranged on a first side of the at least one semiconductor column. At least one second control gate electrode may be arranged on a second side of the at least one semiconductor column. A first charge storage layer may be between the at least one first control gate electrode and the at least one semiconductor column. A second charge storage layer may be between the at least one second control gate electrode and the at least one semiconductor column.

Non-volatile memory device and method of fabricating the same

Methods of reading memory cell data and nonvolatile memory devices, which apply a low voltage to memory cells adjacent to a memory cell from which data may be read are provided. Methods of reading memory cell data of nonvolatile memory device include applying a first voltage to a control gate of a read memory cell from among the plurality of memory cells, applying a third voltage to control gates of memory cell adjacent to the read memory cell, and applying a second voltage to control gates of memory cells other than the read memory cell and the adjacent memory cells.

Growing community of inventors

Suwon-si, South Korea

Young-gu Jin