Qualcomm Incorporated

Avago Technologies Fiber IP (singapore) Pte. Ltd

Integrated Memory Logic, Inc.

Agilent Technologies, Inc.

Avago Technologies General IP Pte, Ltd.

Avago Technologies Limited

Young Gon Kim

Jeongsik Yang

Myunghee Lee

Chiayao S Tung

Shuen-Chin Chang

Yong E Park

Yongwang Ding

Sang-Oh Lee

Robert Elsheimer

Stefano G Therisod

Matthew Scott Abrams

Jianlei Shi

Jae Joon Chang

Kenneth Paul Parker

Beomsup Kim

Cheng-Han Wang

Mazhareddin Taghivand

Shen Wang

Jeff Rearick

Hong Sun Kim

Thinh Cat Nguyen

Tzu-Wang Pan

Benny W H Lai

Emilia Vailun Lei

Sunghyun Park

David Ta-hsiang Lin

Burcin Baytekin

Kamal Aggarwal

Yido Koo

Cindy Yuklin Ng

An RF front end provides high receive selectivity by selectively configuring matching networks within a Time Division Duplex transceiver. One or more elements of the transmit or receive signal paths are configured to perform multiple functions. Each of the functions can be performed in dependence on an operating mode of the RF front end. In some embodiments, one or more elements in the transmit or receive signal paths are reconfigured during receive portions of operation to provide additional receive selectivity.

High selectivity TDD RF front end

The disclosure is directed to compensating for frequency drift in a voltage-controlled oscillator (VCO). Example methods and systems are described which may detect a signal edge associated with a transceiver, and determine whether one or more lock quality signals indicate that the VCO frequency is outside of an specified range, indicating an unacceptable amount of frequency drift. A frequency tuning setting of the VCO may be adjusted based on the one or more lock quality signals, and a determination may be made whether or not the one or more lock quality signals indicate that the VCO frequency has returned to the specified range. The adjustment of the frequency tuning setting of the VCO may be repeated until the VCO frequency returns to the specified range.

Closed loop bank selection for temperature compensation in wireless systems

Reducing coupling and mismatch in multi-core VCOs, including: arranging a plurality of inductors in a plurality of VCO cores in a parallel differential inductor configuration with shared leads to form a single node, wherein the plurality of inductors includes at least a first inductor and a second inductor; connecting power/ground traces to the first inductor from a first side only; and connecting the power/ground traces to the second inductor from another side different from the first side only to avoid making a current loop.

Reducing mismatch caused by power/ground routing in multi-core VCO structure

A transformer is described. The transformer includes a primary coil and a first secondary coil. A first coupling occurs between the first secondary coil and the primary coil. The transformer also includes a second secondary coil. A second coupling occurs between the second secondary coil and the primary coil. The first secondary coil is separated from the second secondary coil to prevent coupling between the first secondary coil and the second secondary coil. A first width of the first secondary coil is configured independently of a second width of the second secondary coil.

Transformer feedback voltage controlled oscillator (VCO)

Certain aspects of the present invention provide methods and apparatus for detecting phase shift between signals, such as local oscillating signals in adjacent transceiver paths. One example circuit for phase detection generally includes a mixer configured to mix a first input signal having a first frequency with a second input signal having a second frequency to produce an output signal having frequency components at the sum of and the difference between the first and second frequencies; a filter connected with the mixer and configured to remove one of the frequency components at the sum of the first and second frequencies, thereby leaving a DC component; and an analog-to-digital converter (ADC) (e.g., a comparator) connected with the filter and configured to determine whether the first input signal is in-phase or out-of-phase with the second input signal based on a comparison between the DC component and a reference signal.

Phase detecting circuit for interchain local oscillator (LO) divider phase alignment

An output portion of a charge pump receives control signals from a phase frequency detector and in response outputs positive current pulses and negative current pulses to a loop filter. A current control portion of the charge pump controls the output portion such that the magnitudes of the positive and negative current pulses are the same. Within the current control portion there is a 'Charge Pump Output Voltage Replica Node' (CPOVRN). The voltage on this CPOVRN is maintained to be the same as a voltage on the charge pump output node. A capacitor leakage compensation circuit indirectly senses the voltage across a leaking capacitor of the loop filter by sensing the voltage on the CPOVRN. The compensation circuit imposes the sensed voltage across a replica capacitor, mirrors a current leaking through the replica, and supplies the mirrored current in the form of a compensation current to the leaking capacitor.

Capacitor leakage compensation for PLL loop filter capacitor

An integrated circuit is described. The integrated circuit includes a global positioning system core that generates a GPS clock signal using an inductor-capacitor voltage controlled oscillator. The integrated circuit also includes a transceiver core configured to use the GPS clock signal. The transceiver core may not include a voltage controlled oscillator.

Clock sharing between cores on an integrated circuit

An integrated circuit is disclosed. The integrated circuit includes a primary coil. The integrated circuit also includes a first secondary coil that acts as a first transformer with the primary coil. The integrated circuit further includes a second secondary coil that acts as a second transformer with the primary coil. The primary coil, the first secondary coil and the second secondary coil have a layout on the integrated circuit to minimize coupling between the first secondary coil and the second secondary coil.

Single differential transformer core

An integrated circuit for providing burn-in current to a laser diode. The integrated circuit includes a laser driver having an output for connection to the laser diode. Burn-in circuitry is formed on the integrated circuit and generates a burn-in current. A switch is formed on the integrated circuit and couples the burn-in current to the laser diode in response to an enable signal.

Integrated circuit having on-chip laser burn-in circuit

An integrated circuit cast on a single die having a plurality of receivers in a receiver region, a plurality of transmitters in a transmitter region, and a spatial separation region having a plurality of n-type and p-type subregions disposed on the single die to separate the transmitter region from the receiver region. The pn-junctions between the n-type and p-type subregions are reverse-biased thereby reducing or eliminating coupling of noise and crosstalk between the transmitter and receiver is reduced.

Integrated multichannel laser driver and photodetector receiver

A method for calibrating a laser transmitter includes (a) detecting an eye diagram of an output from the laser transmitter, (b) determining if the eye diagram is acceptable, (c) if the eye diagram is not acceptable, changing a value of a control signal in the laser transmitter, wherein the control signal sets an amplitude characteristic of a limiting amplifier coupled to a laser driver in the laser transmitter, and (d) repeating steps (a), (b), and (c) until the eye diagram is acceptable.

Eye diagram improving method for laser transmitter

A laser transmitter includes an input stage generating an input signal to a limiting amplifier, the limiting amplifier generating an input signal to a laser driver, and the laser driver generating an input signal to a light source. The limiting amplifier has a control terminal for receiving a control signal that sets an amplitude characteristic of the input signal to the laser driver. The amplitude characteristic may be a common-mode or a peak amplitude of the input signal to the laser driver.

A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle

An apparatus for providing multi-symbol signaling includes a multi-symbol encoder circuit. The multi-symbol encoder circuit is operable to encode data into a plurality of symbols, each symbol uniquely defined by a signal transition and a signal region in a carrier signal. A driver circuit, coupled to the multi-symbol encoder circuit, is operable to drive the carrier signal.

Growing community of inventors

San Jose, CA, United States of America

Young Gon Kim