Skhynix Inc.

Young Geun Yoo

Ki Jun Sung

Jong Hoon Kim

Hyeong Seok Choi

Sang Yong Lee

Jong Hyun Nam

Seung Jee Kim

Pil Soon Bae

A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.

Manufacturing methods semiconductor packages including through mold connectors

Wafer level packages are provided. The wafer level package includes alignment marks disposed at a first surface of a protection wafer, a semiconductor die disposed on the first surface of the protection wafer to be spaced apart from the alignment marks, a first photosensitive dielectric layer covering the semiconductor die and having a flat top surface, and a second dielectric layer covering the flat top surface of the first photosensitive dielectric layer. Redistribution lines are disposed between the first photosensitive dielectric layer and the second dielectric layer and electrically connected to the semiconductor die through first opening portions penetrating the first photosensitive dielectric layer. Outer connectors are disposed on the second dielectric layer and electrically connected to the redistribution lines through second opening portions penetrating the second dielectric layer.

Wafer level packages and electronics system including the same

Semiconductor packages are provided. A semiconductor package may include an embedding substrate including a cavity therein and a connection window in a bottom portion of the cavity. The semiconductor package may include a semiconductor chip disposed in the cavity and coupled to chip connectors, the chip connectors of the semiconductor chip inserted into the connection window. The semiconductor package may include a dielectric layer filling the cavity and the connection window and configured to expose end portions of the chip connectors and to substantially cover the semiconductor chip. Related memory cards and related electronic systems are also provided.

Semiconductor packages

An embedded package includes a first semiconductor chip embedded in a package substrate, a second semiconductor chip disposed over a first surface of the package substrate, and a group of external connection joints disposed on the first surface of the package substrate and between a sidewall of the second semiconductor chip and an edge of the embedded package. Related memory cards and related electronic systems are also provided.

Embedded packages having a connection joint group

A chip stack embedded package includes a first dielectric layer having a multistep cavity therein, a first plurality of semiconductor chips disposed in a first level of the multistep cavity, a second plurality of semiconductor chips disposed in a second level of the multistep cavity, and a second dielectric layer filling the multistep cavity to cover the first and second pluralities of semiconductor chips.

Growing community of inventors

Icheon-si, South Korea

Young Geun Yoo