Samsung Electronics Co., Ltd.

Young-Geun Park

Young-sun Kim

Sung-Tae Kim

Han-Mei Choi

Seung-hwan Lee

Jae-Hyun Yeo

Seung-Hwan Lee

Jae-hyoung Choi

Jong-Cheol Lee

Jae-Soon Lim

Se-hoon Oh

Gab-Jin Nam

Suk-Jin Chung

Cha-young Yoo

Jae-young Ahn

Ha-Jin Lim

Cha-Young Yoo

Jun-Kyu Yang

Jong-Bom Seo

Sun-jung Kim

Yun-Seok Kim

Chang-Hyun Lee

Jungmin Park

Ki-Hyun Hwang

Young-Lim Park

Dong-Chan Kim

Haeryong Kim

Han-jin Lim

Ki-Vin Im

Myoung-Bum Lee

Hojin Lee

Ki-yeon Park

Sang-Yeol Kang

Kyu-Ho Cho

Bong-hyun Kim

Dong-Chul Yoo

Jiwoon Park

Sun-Min Moon

Kyong-Won An

Dong-chul Yoo

Se-hyoung Ahn

Wook-Yeol Yi

Jin-tae Noh

Dong-Woon Shin

Jae-Hyoung Choi

Eun-Ae Chung

Chang-Mu An

Chang-Hwa Jung

Sung-Jung Kim

Byong-ju Kim

Seon-ho Jo

Disclosed is a semiconductor device comprising a substrate, a contact structure that penetrates the substrate, a bottom electrode on the substrate and connected to the contact structure, a dielectric layer that covers the bottom electrode, and a top electrode on the bottom electrode. The dielectric layer separates the top electrode from the bottom electrode. The contact structure includes a lower conductive pattern and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern includes a nitride of a first metal implanted with a dopant.

Semiconductor device and method of fabricating the same

A semiconductor device includes a capacitor including a lower electrode an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABOwhere 'A' is a first metal element and 'B' is a second metal element having a work function greater than that of the first metal element. The dielectric layer includes CDOwhere &#x2018;C&#x2019; is a third metal element and &#x2018;D&#x2019; is a fourth metal element. The lower electrode includes a first layer and a second layer which are alternately and repeatedly stacked. The first layer includes the first metal element and oxygen. The second layer includes the second metal element and oxygen. The dielectric layer is in contact with the lower electrode at a first contact surface the first contact surface corresponding to the second layer.

Semiconductor device and method of manufacturing the same

An integrated circuit (IC) device includes an electrode, a dielectric layer facing the electrode, and a plurality of interface layers interposed between the electrode and the dielectric layer and including a first metal. The plurality of interface layers includes a first interface layer and a second interface layer. An oxygen content of the first interface layer is different from an oxygen content of the second interface layer.

Integrated circuit device having dielectric layer, and method and apparatus for manufacturing the integrated circuit device

A method of manufacturing a semiconductor device includes forming a lower metal layer, forming an interfacial oxide film on the lower metal layer, providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film, performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure, providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor, performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film, and forming an upper metal layer on the dielectric film.

Method for manufacturing semiconductor device

A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

Methods of fabricating memory devices using wet etching and dry etching

Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current.

Methods of forming conductive layer patterns using gas phase cleaning process and methods of manufacturing semiconductor devices

Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.

Methods of manufacturing charge trap type memory devices

A method of fabricating a floating trap type nonvolatile memory device includes forming a cell gate insulating layer on a semiconductor substrate, the cell gate insulating layer being comprised of a lower insulating layer, a charge storage layer and an upper insulating layer sequentially stacked; thermally annealing the cell gate insulating Layer at a temperature of approximately 810&#xb0; C. to approximately 1370&#xb0; C.; and forming a gate electrode on the thermally annealed cell gate insulating layer.

Method of fabricating trap type nonvolatile memory device

Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.

Methods of manufacturing semiconductor devices including metal oxide layers

A method of manufacturing a non-volatile memory device includes forming a tunnel isolation layer forming a tunnel isolation layer on a substrate, forming a conductive pattern on the tunnel isolation layer, forming a lower silicon oxide layer on the conductive pattern, treating a surface portion of the lower silicon oxide layer with a nitridation treatment to form a first silicon oxynitride layer on the lower silicon oxide layer, forming a metal oxide layer on the first silicon oxynitride layer, forming an upper silicon oxide layer on the metal oxide layer, and forming a conductive layer on the upper silicon oxide layer.

Method of manufacturing a non-volatile memory device

In a method of manufacturing a dielectric structure, after a first dielectric layer is formed on a substrate by using a metal oxide doped with silicon, the substrate is placed on a susceptor of a chamber. By treating the first dielectric layer with a plasma in controlling a voltage difference between the susceptor and a ground, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer including a metal oxynitride doped with silicon having enough content of nitrogen is formed on the first dielectric layer. Therefore, dielectric properties of the dielectric structure comprising the first and the second dielectric layers can be improved and a leakage current can be greatly decreased. By adapting the dielectric structure to a gate insulation layer and/or to a dielectric layer of a capacitor or of a non-volatile semiconductor memory device, capacitances and electrical properties can be improved.

Method of forming a dielectric structure having a high dielectric constant and method of manufacturing a semiconductor device having the dielectric structure

In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

Non-volatile memory device and method of manufacturing the same

Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench. A storage electrode is formed in the second trench on the dielectric layer.

Trench capacitors with insulating layer collars in undercut regions

Embodiments of the present invention provide methods of manufacturing memory devices including forming floating gate patterns on a semiconductor substrate having active regions thereon, wherein the floating gate patterns cover the active regions and are spaced apart from the active regions; forming an inter-gate dielectric layer on the semiconductor substrate having the floating gate patterns by alternately stacking a zirconium oxide layer and an aluminum oxide layer at least once, wherein the inter-gate dielectric layer is formed by a deposition process using Ogas as a reactive gas; forming a control gate layer on the inter-gate dielectric layer; and forming a control gate, an inter-gate dielectric layer pattern and a floating gate by sequentially patterning the control gate layer, the inter-gate dielectric layer and the floating gate pattern, wherein the inter-gate dielectric layer pattern and the control gate are sequentially stacked across the active regions, and the floating gate is formed between the active regions and the inter-gate dielectric layer pattern Memory devices, such as flash memory devices are also provided.

Flash memory devices having multilayered inter-gate dielectric layers including metal oxide layers and methods of manufacturing the same

In a method of forming a thin film and methods of manufacturing a gate structure and a capacitor, a hafnium precursor including one alkoxy group and three amino groups, and an oxidizing agent are provided on a substrate. The hafnium precursor is reacted with the oxidizing agent to form the thin film including hafnium oxide on the substrate. The hafnium precursor may be employed for forming a gate insulation layer of a transistor or a dielectric layer of a capacitor.

Method of forming a thin film, method of manufacturing a gate structure using the same and method of manufacturing a capacitor using the same

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Suwon-si, South Korea

Young-Geun Park