Samsung Electronics Co., Ltd.

Young-Don Choi

Byung-Hoon Jeong

Jeong-Don Ihm

Eun-Ji Kim

Jung-June Park

Ji-yeon Shin

Dong-Su Jang

Seon-Kyoo Lee

Go-Eun Jung

Man-Jae Yang

Ki-Tae Park

Jae-Yong Jeong

Kang-Wook Lee

Hyun-Kook Park

Yun-sang Lee

Min-Jae Lee

Dae-Woon Kang

Sang-Lok Kim

Tae-Sung Lee

Hoe-Ju Chung

Hee-Seok Lee

Yong-hoon Kim

Jong-joo Lee

Hoon Shung Lee

Mu-Hui Park

Chang-sik Yoo

Sang-yun Kim

Anil Kavala

Won-chan Kim

Kee-wook Jung

Dae-hoon Na

Young-Hoon Oh

Jeong-don Ihm

Sang-Youb Lee

Ickhyun Song

Ick-Hyun Song

A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

Memory device including on-die-termination circuit

A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory

A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

Defect detection structure of a semiconductor die, semiconductor device including the same and method of detecting defects in semiconductor die

A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

Nonvolatile memory device, memory system including the same and method of operating the same

Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

Nonvolatile memory including duty correction circuit and storage device including the nonvolatile memory

A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

Non-volatile memory device and storage device including the same

Growing community of inventors

Seoul, South Korea

Young-Don Choi