Magnachip Semiconductor, Inc.

Sk Keyfoundry Inc.

Young Chul Seo

Duk Ju Jeong

Kee Sik Ahn

Sung Bum Park

Tae Ho Kim

Kyung Ho Lee

Weon-Hwa Jeong

Yong Hwan Kim

Sung Jin Choi

Chul Geun Lim

An octo mode program and erase operation method to reduce test time in a non-volatile memory device. M/8 word lines corresponding to an octo row, among M word lines, are simultaneously selected, and a write voltage is applied to memory cells connected to M/8 word lines corresponding to the octo row. A voltage that is different from the write voltage is applied to memory cells connected to the rest of word lines, except for M/8 word lines corresponding to the octo row, when the octo signal is applied to an address decoder.

Non-volatile memory octo mode program and erase operation method with reduced test time

An anti-fuse device includes: a well region disposed in a semiconductor substrate; a gate electrode disposed on a gate insulating film on the semiconductor substrate; and a first well bias tap region disposed below the gate insulating film and the gate electrode in the well region, wherein the well bias tap region is doped with dopants of a same conductivity type as the well region.

OTP cell having a reduced layout area

A non-volatile semiconductor storage device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second spaced apart doped regions formed below the gate insulating film and the gate electrode in the semiconductor substrate, wherein a grounded region of the first and second spaced apart doped regions is grounded via a contact.

One time programmable (OTP) cell having improved programming reliability

A one-time programmable non-volatile memory device includes a first conductivity type well region located in a semiconductor substrate, a selection gate electrode and a floating gate electrode located on the substrate, a first doped region located between the selection gate electrode and the floating gate electrode, a second conductivity type source region located on one side of the selection gate electrode, and a second conductivity type drain region located on one side of the floating gate electrode, wherein a depth of the drain region has a depth shallower than that of the first doped region with respect to a top surface of the substrate.

One time programmable non-volatile memory device

Growing community of inventors

Gwangmyeong-si, South Korea

Young Chul Seo