Samsung Electronics Co., Ltd.

Young Chul Cho

Jung Hwan Choi

Jung Bae Lee

Byung In Yoo

Hyo Sun Hwang

Yong Beom Lee

Gyeong Ja Jang

Young Don Choi

Jae Woo Park

Young Jin Jeon

Seung Jin Park

Yoon Joo Eom

Hyeok Jun Choi

Yong Cheol Bae

A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

Memory device, operating method of the memory device and memory system comprising the memory device

A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Memory interface with selectable connections for input receiver circuits based on operating mode

High/low speed mode selection for output driver circuits of a memory interface

Operating method of input/output interface

An interactive method includes displaying image content received through a television (TV) network, identifying an object of interest of a user among a plurality of regions or a plurality of objects included in the image content, and providing additional information corresponding to the object of interest.

Method of providing user specific interaction using device and digital television (DTV), the DTV, and the user device

Input/output interface

A three-dimensional (3D) display device for providing an input-output interface using a dynamic magnetic field control is disclosed, the device including a display unit to display a 3D image, a magnetic field generation unit to generate a magnetic field, and a control unit to dynamically control the magnetic field generation unit to generate a 3D magnetic field associated with the 3D image.

Three-dimensional (3D) display device for providing input-output interface using dynamic magnetic field control and method thereof

A small signal receiver includes a first current adjustment circuit connected between a first power supply voltage terminal and a first node to provide current in response to a self-bias signal, a self-biased differential amplifier connected between the first node and a second node to compare an input signal with a reference voltage, provide the self-bias signal to a self-biasing node and output an output signal through an output node, and a second current adjustment circuit connected between the second node and a second power supply voltage terminal to sink current at the second node in response to the self-bias signal. The self-biased differential amplifier includes a swing stabilizing block connected between an input node to which the input signal is applied and the self-biasing node to stabilize the input signal compared with the reference voltage.

Small signal receiver and integrated circuit including the same

Method of providing user specific interaction using device and digital television(DTV), the DTV, and the user device

A semiconductor memory device has a clock input buffer that is turned 'on' or 'off' in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal.

Semiconductor memory devices having internal clock signals and memory systems including such memory devices

An output driving circuit includes a first pull-up transistor, a first pull-down transistor and a second pull-down transistor. The first pull-up transistor is configured to generate a first output signal at the output node in response to a first control signal. The first pull-down transistor is configured to generate a second output signal at the output node in response to a second control signal. The second pull-down transistor is configured to connect the output node to the first ground voltage in response to a third control signal. The memory device including the output driving circuit may be insensitive to noise and may have little data transmission error.

Growing community of inventors

Yongin-si, South Korea

Young Chul Cho